Ultra-low-power 2.4 GHz image-rejection low-noise amplifier

An ultra-low-power image-rejection low-noise amplifier (IR-LNA) for 2.4 GHz ZigBee applications based on 0.18 /spl mu/m CMOS technology is presented. By using the third-order active notch filter the proposed IR-LNA can achieve high image-rejection ratio. Measurements show 12 dB gain, 1.8 dB noise figure, 38 dB image-rejection, -3 dBm input third-order intercept point, -18 and -19 dB input and output return loss while dissipating 0.6 mA from a supply voltage of 1.5 V.     

X波段低噪声放大器的设计

为了实现X波段的低噪声放大器,介绍了按最小噪声系数设计,采用两级级联,利用Eudyna公司的HEMT晶体管设计制作的低噪声放大器。通过专用微波电路设计软件(AWR),对该电路的稳定系数、功率增益、噪声系数、驻波比、匹配网络等进行了仿真分析。根据分析结果制作的X波段LNA取得了如下指标:在9.5～10.5 GHz频带内,功率增益大于22 dB,噪声系数小于1.5 dB,输入输出驻波小于1.7。     

可变增益低噪声放大器的设计与实现

传统结构的低噪声放大器的噪声系数较高,增益平坦性较差。为了解决该问题,设计了可变增益低噪声放大器,其由高增益模块、中间增益模块和低增益模块构成。将有源负反馈低噪声放大器作为放大器的高增益放大模块,采集微弱的输入信号。中间增益模块通过电阻分压衰减器实现输入信号的衰减处理,确保总体放大器具有较高的线性度。低增益模块通过衰减器完成相关工作,可采集到强信号,避免三阶交调量对系统信噪比的不利干扰。实验结果说明,设计的低噪声放大器在电压增益、噪声系数和三阶交调量三方面的性能都较优。     

基于ADS的微波低噪声放大器的设计与仿真

低噪声放大器包括输入匹配网络、微波晶体管放大器和输出匹配网络.微波晶体管放大器是设计中的核心部分.根据低噪声放大器设计的原理,提出技术指标要求,设计一个5GHz单级低噪声放大器,经过技术指标分析,采用Fujitsu公司的FHX35LG型HEMT场效应管晶体管.阐述了如何利用Agilent公司的ADS软件进行分析和优化设...     

Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme

The pin-to-pin electrostatic discharge (ESD) stress was one of the most critical ESD events for differential input pads. The pin-to-pin ESD issue for a differential low-noise amplifier (LNA) was studied in this work. A new ESD protection scheme for differential input pads, which was realized with cross-coupled silicon-controlled rectifier (SCR), was proposed to protect the differential LNA. The cross-coupled-SCR ESD protection scheme was modified from the conventional double-diode ESD protection scheme without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad in this cross-coupled-SCR ESD protection scheme, so the pin-to-pin ESD robustness can be improved. The test circuits had been fabricated in a 130-nm CMOS process. Under pin-to-pin ESD stresses, the human-body-model (HBM) and machine-model (MM) ESD levels of the differential LNA with the cross-coupled-SCR ESD protection scheme are >8 kV and 800 V, respectively. Experimental results had shown that the new proposed ESD protection scheme for the differential LNA can achieve excellent ESD robustness and good RF performances.     

一款高增益宽带低噪声放大器的设计

采用0.5μm GaAs E-PHEMT工艺设计了一款0.5～5 GHz高增益宽带低噪声放大器芯片.该放大器采用三级共源结构,运用负反馈技术有效地进行了输入输出阻抗匹配,针对高频增益不足问题,在共栅晶体管的栅极到地之间增加栅极电容,提高了高频增益,改善了增益平坦度,拓展了带宽.同时,放大器前两级应用电流复用技术,大大降...     

CMOS single-ended-to-differential low-noise amplifier

In this work, a low-power single-ended-to-differential low-noise amplifier (LNA) is reported. The circuit has been designed and optimized to be included in an IEEE 802.15.4 standard receiver. In order to minimize power consumption, active loads and currents mirrors have been replaced by optimized inductors and transformers. Moreover, an exhaustive study of the mixed-mode parameters has been carried out, enabling the definition of single-ended figures of merits in terms of mixed-mode S-parameters. The LNA has been implemented using a 0.35 μm RFCMOS technology. Performances are a noise figure of 4.3 dB, a power gain of 21 dB, and a phase balance of 180±1°. Regarding non-linear behaviour, the obtained 1 dB-compression point obtained is −9.5 dB m while intermodulation intercept point is −3 dB m, dissipating 6 mA from 1.5 V supply voltage.     

基于自适应遗传算法的低噪声放大器设计

低噪声放大器是射频接收系统的关键组成部分,决定了系统的噪声特性,直接影响接收灵敏度。提出一种利用自适应遗传算法设计低噪声放大器匹配电路的思路,自动优化交叉概率和变异概率,避免了易早熟的缺点。采用这一算法进行了放大器设计实验,放大器具有较低的噪声系数、较高的放大增益,以及较好的带外抑制效果。实验结果表明实测和软件仿真性能吻合较好,证明了自适应遗传算法设计的可靠性。     

Ultra-wideband SiGe low-noise amplifier

A low-noise amplifier (LNA) for ultra-wideband (UWB) is presented. The LNA, consisting of two gain stages in multiple feedback loops, achieves a flat power gain of a nominal 20 dB and a noise figure of 2.8-4.7 dB over the 3.1-10.6 GHz UWB band. Implemented in a 0.25 /spl mu/m SiGe BiCMOS process, the amplifier occupies 0.34 mm/sup 2/ and draws 11 mA from a 2.7 V supply.     

High-dynamic-range low-noise microwave amplifier

The operation of a high-dynamic-range parametric amplifier is described. The varactor is a GaAs p?n junction with an n type layer suitable for operation as a K band transferred-electron oscillator (t.e.o.). A dynamic range of approximately 177 dB/Hz and a noise figure of less than 2 dB were measured at C band. The tests were made to show the feasibility of high-dynamic-range low-noise microwave amplification for radar-receiver applications, and to establish the feasibility of high-performance monolithic multifunction chips from the material standpoint.     

A low-noise amplifier with parallel integrated-circuit transistors

Low-noise transistor performance is achieved by paralleling a number of general-purpose integrated transistors. The primary effect of paralleling is to reduce the equivalent base resistance. A noise figure of 2.5 dB with a 50-/spl Omega/ source impedance is measured.     

Wideband HEMT MMIC low-noise amplifier with temperaturecompensation

A wideband low-noise pseudomorphic HEMT MMIC variable-gain amplifier has been designed and fabricated. The amplifier has a nominal gain of 13 dB across the band 2-20 GHz, with gain flatness better than ±0.4 dB. The noise figure is less than 3 dB across the band 6-16 GHz. An on-chip temperature-sensing diode is used to provide a linear temperature correction which has been used to reduce the gain variation of the amplifier by a factor of 2 across the temperature range -50°C to +95°C     

A low-noise NMOS operational amplifier

NMOS operational amplifiers are known to have low-voltage gain and a poor noise performance. A new circuit technique is described which improves these parameters to achieve a typical DC voltage gain of 40000 and an average noise of 57 (nV/Hz/SUP 1/2/) over a 3 kHz bandwidth, with a total power dissipation of 6 mW.     

A low-noise high-precision operational amplifier

A low-noise high-precision operational amplifier has recently been fabricated in monolithic form with dielectric isolation. The amplifier exhibits a V/SUB OS/ of 10 /spl mu/V, V/SUB OS/T/SUB c/ of 0.3 /spl mu/V//spl deg/C, voltage gain of 140 dB with a 600 /spl Omega/ load, and an input noise voltage of 9 nV//spl radic/Hz. The settling time to within 0.01 percent of final value is 15 /spl mu/s for a 10 V pulse.     

Design and performance of a low-noise charge-detection amplifier for VPCCD devices

This paper describes the design and performance of a low-noise amplifier used with virtual phase charge-coupled devices. Topology of the detection node, details of the operation, and computer simulations for critical device parameters are presented. Attention is focused on the noise performance and charge-detection sensitivity. A simple noise model is developed and used to derive an expression for the noise equivalent number of electronsN_eewhich is then used to optimize the amplifier design. Finally, predictions obtained from the model are compared with measurements, and conclusions are drawn for the maximum attainable performance. In addition to the thermally generated noise, usually measured in buried-channel MOS transistors, an excess noise is sometimes seen at moderate to large drain biases. This phenomenon is also observed in this amplifier. However, an explanation for the effect, confirmed by measurement, is presented and a method to avoid degradation of the amplifier performance is found.     

基于ADS宽带微波低噪声放大器设计与仿真

文章主要研究低噪声放大器在宽频带范围内增益平坦度低、阻抗匹配差的问题。选用Avago公司生产的具有高动态范围和低噪声特性的PHEMT器件ATF-38143晶体管,采用自给偏置共源,负反馈结构,基于ADS仿真设计完成一款两级级联的宽带低噪声放大器。该放大器利用源极串联反馈电感和输入端接双支节微带线的匹配方法。仿真结果显示放大器在1.0～3.0 GHz的频带范围内,输入输出回波损耗均小于-10 dB;系统稳定性因子K> 1;噪声系数为(1.6±0.4)dB;最大增益为26.5 dB,增益平坦度缩小到±0.5 dB。     

一种基于共面波导的0.14 THz低噪声放大器设计

为解决低噪声放大器设计中过渡电路的实现问题,对基于共面波导的波导-平面电路过渡形式进行改进和优化,设计了一种工作频率为0.14 THz,带宽10 GHz的低噪声放大器。通过仿真,得到了输入输出回波损耗小于-27 dB,插入损耗小于0.1 dB 的结果。此种方法能够很好地实现信号在不同传输线形式间的转换,并得到了无源测试验证。     

一种低噪声高增益零中频放大器的设计与实现

文中介绍了一种低噪声的零中频放大器的设计与实现,通过选用合适的集成运算放大器芯片,完成低噪声、高增益并具备滤波效果的零中频放大器的设计.阐述了运放芯片的选择依据,电路的工作原理并使用Cadence制板软件完成了电路板的设计.实际测试结果表明,该电路工作稳定,噪声、增益、滤波特性等效果均很好.     

CMOS low-noise amplifier design optimization techniques

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the noise parameter equations, this paper provides clear understanding of the design principles, fundamental limitations, and advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very low-power folded-cascode LNA is implemented based on 0.25-/spl mu/m CMOS technology for 900-MHz Zigbee applications. Measurement results show the noise figure of 1.35 dB, power gain of 12 dB, and input third-order intermodulation product of -4dBm while dissipating 1.6 mA from a 1.25-V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.     

A GaAs monolithic low-noise broad-band amplifier

Describes the design, fabrication, and performance of GaAs monolithic low-noise broad-band amplifiers intended for broadcast receiver antenna amplifier, IF amplifier, and instrumentation applications. The process technology includes the use of Czochralski-grown semiinsulating substrates, localized implantation of ohmic and FET channel regions, and silicon nitride for passivation and MIM capacitors. The amplifiers employ shunt feedback to obtain input matching and flat broad-band response. One amplifier provides a gain of 24 dB, bandwidth of 930 Mhz, and noise figure of 5.0 dB. A second amplifier provides a gain of 17 dB, bandwidth of 1400 MHz, and noise figure of 5.6 dB. Input and output VSWR's are typically less than 2:1 and the third-order intercept points are 28 and 32 dB, respectively. Improved noise figure and intercept point can be achieved by the use of external RF chokes.