A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a dc input and outputs a doubled dc voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pairs generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by spice with TSMC 0.35-μm CMOS technology and operates with a 2.7 V to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.     

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.     

A Clock Generator for High-Speed High-Resolution Pipelined A/D Converter Zhao Lei(赵磊) , Yang Yintang(杨银堂), Zhu Zhangming(朱樟明), Liu Lianxi(刘帘羲)

A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented.The circuit is realized by a delay locked loop(DLL),and a new differential structure is used to improve the precision of the charge pump.Meanwhile,a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition.The proposed circuit,designed by SM1C 0.18μm 3.3 V CMOS technology,is used as a clock generator for a 14 bit 100 MS/s pipelined ADC.The simulation results have shown that the duty cycle ranged from 10%to 90%and can be adjusted.The average duty cycle error is less than 1%.The lock-time is only 13 clock cycles.The active area is 0.05 mm2 and power consumption is less than 15 mW.     

一种高可靠性、低功耗单节锂电池保护电路

A single lithium-ion battery protection circuit with high reliability and low power consumption is proposed.The protection circuit has high reliability because the voltage and current of the battery are controlled in a safe range.The protection circuit can immediately activate a protective function when the voltage and current of the battery are beyond the safe range.In order to reduce the circuit’s power consumption,a sleep state control circuit is developed.Additionally,the output frequency of the ring oscillation can be adjusted continuously and precisely by the charging capacitors and the constant-current source.The proposed protection circuit is fabricated in a 0.5 m mixed-signal CMOS process.The measured reference voltage is 1.19 V,the overvoltage is 4.2 V and the undervoltage is 2.2 V.The total power is about 9 W.     

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells.If we want to reduce the overall power in the memory system,we have to work on the input circuitry of memory architecture i.e.row and column decoder.In this research work,low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed.In this work,the comparison of cluster DECODER,body bias DECODER,source bias DECODER,and source coupling DECODER are designed and analyzed for memory array application.Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool.Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92％ and static energy by 99.92％ at a supply voltage of 1.2 V.The proposed circuit also improves dynamic power dissipation by 5.69％,dynamic PDP/EDP 65.03％ and delay 57.25％ at 1.2 V supply voltage.     

Design of low-voltage and low-power fully integrated filter based on log-domain current-mode integrator

In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range. The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.     

高效率低电磁干扰的升压型DC–DC转换器

A synchronous boost DC-DC converter with an adaptive dead time control （DTC） circuit and antiringing circuit is presented. The DTC circuit is used to provide adjustable dead time and zero inductor current detection for power transistors and therefore, a high efficiency is achieved by minimizing power losses, such as the shoot-through current loss, the body diode conduction loss, the charge-sharing loss and the reverse inductor current loss. Simultaneously, a novel anti-ringing circuit controlled by the switching sequence of power transistors is developed to suppress the ringing when the converter enters the discontinuous conduction mode （DCM） for low electromagnetic interference （EMI） and additional power savings. The proposed converter has been fabricated in a 0.6 #m CDMOS technology. Simulation and experimental results show that the power efficiency of the boost converter is above 81% under different load currents from 10 to 250 mA and a peak efficiency of 90% is achieved at about 100 mA. Moreover, the ringing is easily suppressed by the anti-ringing circuit and therefore the EMI noise is attenuated.     

采用金属耦合电容实现级间匹配的射频功率放大器

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available,especially no high density capacitor.To address this problem,a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process.This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal（MIM） capacitor regarding their capacitor density.Detailed simulations are carried out for the leakage,the voltage dependency,the temperature dependency,and the quality factor between an inter-metal shuffled（IMS） capacitor and an MIM capacitor.Finally,an IMS capacitor is chosen to perform the inter-stage matching.The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application.The PA occupies 370 × 200 μm^2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.     

基于石英基片的W波段高输出功率肖特基二极管倍频器

W-band quartz based high output power fix-tuned doublers are analyzed and designed with planar Schot- tky diodes. Full-wave analysis is carried out to find diode embedding impedances with a lumped port to model the nonlinear junction. Passive networks of the circuit, such as the low pass filter, the E-plane waveguide to strip transitions, input and output matching networks, and passive diode parts are analyzed by using electromagnetic simulators, and the different parts are then combined and optimized together. The exported S-parameters of the doubler circuit are used for multiply efficiency analysis. The highest measured output power is 29.5 mW at 80 GHz and higher than 15 mW in 76-94 GHz. The highest measured efficiency is 11.5% at 92.5 GHz, and the typical value is 6.0% in 70-100 GHz.     

Dual-Voltage Single-Rail Dynamic DPA-Resistant Logic Based on Charge Sharing Mechanism

Differential power analysis (DPA) has become a major system security concern.To achieve high levels of security with low power and die area costs,a novel Dual-voltage single-rail dynamic logic (DSDL) design is proposed.The proposed scheme can reduce power dissipation and obtain extremely well-balanced power consumption.The charge sharing mechanism is used for voltage transfer in the internal nodes during the evaluation of the design.Dual power supply voltages are used with positive feedback to speed up the evaluation process.A 4-bit micro Substitution box (SBOX) of the Advanced encryption standard (AES) algorithm has been implemented to verify the security of the proposed logic design.The experimental results proved the security and the efficiency of the proposed DSDL,which can reduce power dissipation by up to 20％ and occupies at most 83％ of the silicon area when compared with previous state-of-the-art countermeasures.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.     

EEFA： Energy Efficiency Frame Aggregation Scheduling Algorithm for IEEE 802.11n Wireless Network

Packet size is restricted due to the error-prone wireless channel which drops the network energy utilization. Furthermore, the frequent packet retransmissions also lead to energy waste. In order to improve the energy efficiency of wireless networks and save the energy of wireless devices, EEFA （Energy Efficiency Frame Aggregation）, a frame aggregation based energy-efficient scheduling algorithm for IEEE 802.11n wireless network, is proposed. EEFA changes the size of aggregated frame dynamically according to the frame error rate, so as to ensure the data transmission and retransmissions completed during the TXOP and reduce energy consumption of channel contention. NS2 simulation results show that EEFA algorithm achieves better performance than the original frame-aggregation algorithm.     

SDN-Based Data Offioading for 5G Mobile Networks

The rapid growth of 3G/4G enabled devices such as smartphones and tablets in large numbers has created increased demand formobile data services.Wi-Fi offloading helps satisfy the requirements of data-rich applications and terminals with improved multi-media.Wi-Fi is an essential approach to alleviating mobile data traffic load on a cellular network because it provides extra capaci-ty and improves overall performance.In this paper,we propose an integrated LTE/Wi-Fi architecture with software-defined net-working(SDN)abstraction in mobile backhaul and enhanced components that facilitate the move towards next-generation 5G mo-bile networks.Our proposed architecture enables programmable offloading policies that take into account real-time network condi-tions as well as the status of devices and applications.This mechanism improves overall network performance by deriving real-time policies and steering traffic between cellular and Wi-Fi networks more efficiently.     

应力和电阻率可控的适用于高品质因子MEMS器件的原位掺硼LPCVD多晶硅薄膜

The simultaneous control of residual stress and resistivity of polysilicon thin films by adjusting the deposition parameters and annealing conditions is studied. In situ boron doped polysilicon thin films deposited at 520 ℃ by low pressure chemical vapor deposition （LPCVD） are amorphous with relatively large compressive residual stress and high resistivity. Annealing the amorphous films in a temperature range of 600-800 ℃ gives polysilicon films nearly zero-stress and relatively low resistivity. The low residual stress and low resistivity make the polysilicon films attractive for potential applications in micro-electro-mechanical-systems （MEMS） devices, especially in high resonance frequency （high-f） and high quality factor （high-Q） MEMS resonators. In addition, polysilicon thin films deposited at 570 ℃ and those without the post annealing process have low resistivities of 2-5 mΩ·cm. These reported approaches avoid the high temperature annealing process （〉 1000 ℃）, and the promising properties of these films make them suitable for high-Q and high-f MEMS devices.     

Large-signal characterizations of DDR IMPATT devices based on group Ⅲ-Ⅴ semiconductors at millimeter-wave and terahertz frequencies

Large-signal （L-S） characterizations of double-drift region （DDR） impact avalanche transit time （IM- PATT） devices based on group III-V semiconductors such as wurtzite （Wz） GaN, GaAs and InP have been carried out at both millimeter-wave （mm-wave） and terahertz （THz） frequency bands. A L-S simulation technique based on a non-sinusoidal voltage excitation （NSVE） model developed by the authors has been used to obtain the high frequency properties of the above mentioned devices. The effect of band-to-band tunneling on the L-S properties of the device at different mm-wave and THz frequencies are also investigated. Similar studies are also carried out for DDR IMPATTs based on the most popular semiconductor material, i.e. Si, for the sake of comparison. A compara- tive study of the devices based on conventional semiconductor materials （i.e. GaAs, InP and Si） with those based on Wz-GaN shows significantly better performance capabilities of the latter at both mm-wave and THz frequencies.     

Survivable Virtual Network Mapping Using Optimal Backup Topology in Virtualized SDN

Software-Defined Network architecture offers network virtualization through a hypervisor plane to share the same physical substrate among multiple virtual networks. However, for this hypervisor plane, how to map a virtual network to the physical substrate while guaranteeing the survivability in the event of failures, is extremely important. In this paper, we present an efficient virtual network mapping approach using optimal backup topology to survive a single link failure with less resource consumption. Firstly, according to whether the path splitting is supported by virtual networks, we propose the OBT-I and OBT-II algorithms respectively to generate an optimal backup topology which minimizes the total amount of bandwidth constraints. Secondly, we propose a Virtual Network Mapping algorithm with coordinated Primary and Backup Topology （VNM-PBT） to make the best of the substrate network resource. The simulation experiments show that our proposed approach can reduce the average resource consumption and execution time cost, while improving the request acceptance ratio of VNs.     

用于ZigBee的2.4GHz低功耗双增益低噪声放大器

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.     

应用于低中频和零中频DVB调谐器中8阶信道滤波器设计

An eighth order active-RC filter for low-IF and zero-IF DVB tuner applications is presented, which is implemented in Butterworth biquad structure. An automatic frequency tuning circuit is introduced to compensate the cut-off frequency variation using a 6-bit switched-capacitor array. Switched-resistor arrays are adopted to cover different cut-off frequencies in low-IF and zero-IF modes. Measurement results show that precise cut-off frequencies at 2.5, 3, 3.5 and 4 MHz in zero-IF mode, 5, 6, 7 and 8 MHz in low-IF mode can be achieved, 60 dB frequency attenuation can be obtained at 20 MHz, and the in-band group delay agrees well with the simulation. Two-tone testing shows the in-band IM3 achieves -52 dB and the out-band IM3 achieves -55 dB with -11 dBm input power. This proposed filter circuit, fabricated in a SMIC 0.18μm CMOS process, consumes 4 mA current with 1.8 V power supply.     

Distributed Power Control for Energy Conservation in Hybrid Cellular Network with Device-to-Device Communication

Device-to-Device （D2D） com- munication has been proposed as a promising implementation of green communication to benefit the existed cellular network. In order to limit cross-tier interference while explore the gain of short-range communication, we devise a series of distributed power control （DPC） schemes for energy conservation （EC） and enhancement of radio resource utilization in the hybrid system. Firstly, a constrained opportunistic power control model is built up to take advantage of the interference avoidance methodology in the presence of service requirement and power constraint. Then, biasing scheme and admission control are added to evade ineffective power consumption and maintain the feasibility of the system. Upon feasibility, a non-cooperative game is further formulated to exploit the profit in EC with minor influence on spectral efficiency （SE）. The convergence of the DPC schemes is validated and their performance is confirmed via simulation results.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.