Modelling delay and crosstalk in VLSI interconnect for electricalsimulation

A method for extracting the multi-pen equivalent network of a system of m distributed RC lines is presented. The technique enables the time delays and crosstalk between interconnects to be efficiently analysed by employing conventional circuit simulators     

A multilevel parasitic interconnect capacitance modeling andextraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays     

An empirical three-dimensional crossover capacitance model formultilevel interconnect VLSI circuits

We develop an empirical model for the crossover capacitance induced by the wire crossings in VLSI with multilevel metal interconnects. The crossover capacitance, which is formed in any three adjacent layers and of a three-dimensional (3-D) nature, is derived in closed form as a function of the wire geometry parameters. The total capacitance on a wire passing many crossings can then be easily determined by combining the crossover capacitance with the two-dimensional (2-D) intralayer coupling capacitance defined on a same layer. The model agrees well with the numerical field solver (with a 6.7% root-mean-square error) and measurement data (with a maximum error of 4.17%) for wire width and spacing down to 0.16 μm and wire thickness down to 0.15 μm. The model is useful for VLSI design and process optimization     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

Tradeoff between interconnect capacitance and RC delay variationsinduced by process fluctuations

This paper describes the influence of the process fluctuations such as the critical dimension (CD) variation upon the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. An interconnect design guideline to reduce C and/or RC delay variations is proposed. Also, C and RC delay variations for Cu interconnect are discussed     

Optimization study of VLSI interconnect parameters

In this paper, we present the results of optimizing interconnect parameters to satisfy chip-level targets in future device generations. The optimization approach used is based on existing system-level models and can optimize the number of wire levels, speed, chip size, and power in sequence, with the optimization variables being all interconnect parameters such as pitches, thicknesses, etc. We also study the trade-offs resulting from various interconnect process limitations and choices. The findings of this study, in brief, are: 1) while the thickness of the interlayer dielectric (ILD) can be scaled without adverse effects on speed so that the hole aspect ratio is held constant at about 3.0 across generations, it is important to provide extremely thick ILD films in excess of 4 pm in the upper wire levels, 2) while the maximum wire thickness can be safely held to about 2 μm in the upper wire levels, extremely thin wires of less than 0.1 pm thickness will soon be needed in the lower wire levels to reduce capacitance, 3) while wire resistivity reduction is desirable it is much more important to reduce the ILD dielectric constant aggressively, and 4) chip size constraints can impact the speed extremely and need to considered carefully. These results can be used to construct an optimal interconnect technology roadmap and can be an invaluable aid in guiding interconnect process development     

VLSI interconnect issues in definitive and stochastic environments

A system designer needs to estimate the behavior of a system interconnection based on different patterns of switching which happen around an interconnect. Two different scenarios are supposed to estimate the effect of interconnect issues on system performance. First, based on a normalization technique for decreasing the number of a transfer function variables, a definitive environment for one interconnect is considered and an optimized look-up-table for the wire time delay is generated. Using some sampling methods, fast accessible look-up-tables are proposed for CAD tools in very simple and small one. A 4×4×4 table for the wire delay is introduced which results in very fast estimation. The average and maximum error of this look-up-table is less than 1% and 7.7% respectively, compared to HSPICE results. Second, the statistical environment of a wire in a BUS configuration is studied for all possible different switching patterns happening for the wires. Estimating the BUS main problems, including power consumption, crosstalk, and propagation delay for a random environment, which a wire senses in wide BUS, is only possible with statistical parameters like mean and variance. All simulations are done considering both wire inductive and capacitive couplings in HSPICE. Also, the secondary effect of crosstalk on propagation delay and power consumption is considered. The simulation results show 3.81% of BUS input switching can lead to a wrong decision on its wire load due to the crosstalk induced voltages in 90 nm technology. The average induced crosstalk aware power consumption is 94 μW. Also, the average of maximum crosstalk on the load can be as high as 25% of the V_dd.     

An on-chip, interconnect capacitance characterization method withsub-femto-farad resolution

A simple, accurate method of measuring interconnect capacitances is presented. The test structure has excellent resolution, needs only DC measurements, and is compact enough for scribe-line implementation. These qualities make it suitable for measurement-based, interconnect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices. The entire characterization scheme is demonstrated for a production 0.5 μm, three-level metal technology. The method not only provides an accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlevel dielectric (ILD) thickness and drawn width reductions for process control as well     

VLSI随机工艺变化下互连线建模与延迟分析

目前互连线的工艺变化问题已成为影响超大规模集成电路性能的重要因素.考虑了互连线工艺变化的空间相关性,将工艺参数变化建模为具有自相关性的随机过程,采用数值仿真及拟合方法得到寄生参数的近似表达式,最后基于Elmore延迟度量分析了随机工艺变化对互连延迟的影响,提出了工艺变化下互连延迟统计特性的估算方法,并通过仿真实验对方法的有效性进行了验证.     

A frequency-domain approach to interconnect crosstalk simulation and minimization

A frequency-domain approach to efficiently simulate and minimize the crosstalk between high speed interconnects is proposed in this paper. Several methods for modeling coupled microstrip transmission lines are discussed. Several possible simulation strategies are also considered. A straightforward yet rigorous frequency-domain approach is followed. This approach can be used for linearly and non-linearly terminated microstrip coupled lines, since it exploits the harmonic balance technique. A typical example of microstrip interconnects is simulated and the results are compared with those obtained in previous work by other authors using time-domain methods. The simulation method proposed in this work yields good accuracy. A crosstalk minimization problem is formulated and solved following the method proposed.     

Design of tapered buffers with local interconnect capacitance

This paper presents a design methodology and analytic relationships for the optimal tapering of cascaded buffers which consider the effects of local interconnect capacitance. The method, constant capacitance-to-current ratio tapering (C³RT), is based on maintaining the capacitive load to current drive ratio constant, and therefore, the propagation delay of each buffer stage also remains constant. Reductions in power dissipation of up to 22% and reductions in active area of up to 46%, coupled with reductions in propagation delay of up to 2%, as compared with tapered buffers which neglect local interconnect capacitance, are exhibited for an example buffer system     

Minimization of delay and crosstalk in high-speed VLSIinterconnects

Design optimization of time responses of high-speed VLSI interconnects modeled by distributed coupled transmission line networks is presented. The problem of simultaneous minimization of crosstalk, delay and reflection is formulated into minimax optimization. Design variables include physical/geometrical parameters of the interconnects and parameters in terminating/matching networks. A recently published simulation and sensitivity analysis technique for multiconductor transmission lines is expanded to directly address the VLSI interconnect environment. The new approach permits efficient physical/geometrical oriented interconnect design using exact gradient based minimax optimization. Examples of interconnect optimization demonstrate significant reductions of crosstalk, delay, distortion and reflection at all vital connection ports. The technique developed is an important step towards optimal design of circuit interconnects for high-speed digital computers and communication systems     

Modeling of multiconductor buses and analysis of crosstalk,propagation delay and pulse distortion in high speed GaAs logic circuits

Crosstalk, propagation delay, pulse distortion in multiconductor buses for high-speed GaAs logic circuits are analyzed. A simple but accurate quasi-TEM model of the bus is developed, and a critical analysis is carried out both on the accuracy of different approximate lumped and distributed models and on the impact of such approximations on the time-domain response. Results on the behavior of multiconductor buses in the presence of realistic input waveforms, are presented and design criteria are obtained     

Optimization of interconnect thickness for minimum propagation delays in VLSI

Simple analytical formulation has been used to compute the optimum thickness of a set of interconnect materials having different resistivities for obtaining minimum propagation delay in small scale VLSI. The analytical formulae incorporate two- and three-dimensional fringing effects on resistance and capacitance calculation of long interconnecting lines in complex circuits. Variations of different parameters have been plotted for 0.5 λ and 0.1 λ design rules.     

Modelling noise and delay in VLSI circuits

New models for estimating delay and noise in VLSI circuits, based on closed form expressions for the first and second moment of the impulse response in coupled RC trees are reported. The effect of crosstalk on delay and noise can be accurately estimated with a complexity only marginally higher than the Elmore delay.     

Investigation of interconnect capacitance characterization usingcharge-based capacitance measurement (CBCM) technique andthree-dimensional simulation

This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure     

Fitted Elmore delay: a simple and accurate interconnect delay model

In this brief, we present a new interconnect delay model called fitted Elmore delay (FED). FED is generated by approximating HSPICE delay data using a curve fitting technique. The functional form used in curve fitting is derived based on the Elmore delay (ED) model. Thus, our model has all the advantages of the ED model. It has a closed-form expression as simple as the ED model and is extremely efficient to compute. Interconnect optimization with respect to design parameters can also be done as easily as in the ED model. In fact, most previous algorithms and programs based on ED model can use our model without much change. Most importantly, FED is significantly more accurate than the ED model. The maximum error in delay estimation is at most 2% for our model, compared to 8.5% for the scaled ED model. The average error is less than 0.8%. We also show that FED can be more than 10 times more accurate than the ED model when applied to wire sizing.     

VLSI中互连线工艺变化的若干问题研究进展

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,互连线的工艺变化已成为影响集成电路性能的重要因素.针对该问题,结合作者的研究工作,综述了目前国内外互连线工艺变化若干关键问题的研究进展情况,重点介绍工艺变化条件下互连线寄生电参数及其传输性能的研究方法,并分析不同技术的特点和局限性.最后展望了互连线工艺变化问题今后的研究发展方向.     

Bus encoder design for reduced crosstalk,power and area in coupled VLSI interconnects

This research work presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method is used to reduce inter-wire coupling, which is actually responsible for crosstalk, delay and power dissipation in coupled interconnects. The proposed method focuses on simplified and improved encoder circuit for 4, 8 and 16 coupled lines. In past, the researchers developed encoders that usually focused on minimizing power dissipation and/or crosstalk, thereby paying heavy penalty in terms of chip area. However, the proposed encoder and decoder while significantly reducing crosstalk demonstrates an overall reduction of power dissipation by 68.76% through drastically limiting switching activity. Furthermore, while reducing the complexity, chip area and transistor count of the circuit is reduced by more than 57%.