Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--slow-to-rise and slow-to-fall--are considered as well as delayed transitions from isolating signal state high impedance to binary states 0 and 1 and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.     

Mobility Management for Hierarchical Wireless Networks

In this paper, we consider the mobility management in large, hierarchically organized multihop wireless networks. The examples of such networks range from battlefield networks, emergency disaster relief and law enforcement etc. We present a novel network addressing architecture to accommodate mobility using a Home Agent concept akin to mobile IP. We distinguish between the physical routing hierarchy (dictated by geographical relationships between nodes) and logical hierarchy of subnets in which the members move as a group (e.g., company, brigade, battalion in the battlefield). The performance of the mobility management scheme is investigated through simulation.     

Recursive identification algorithms

Mechanisms for adapting models, filters, decisions, regulators, and so on to changing properties of a system or a signal are of fundamental importance in many modern signal processing and control algorithms. This contribution describes a basic foundation for developing and analyzing such algorithms. Special attention is paid to the rationale behind the different algorithms, thus distinguishing between optimal algorithms and ad hoc algorithms. We also outline the basic approaches to performance analysis of adaptive algorithms.     

Predictive Caching Strategy for On-Demand Routing Protocols in Wireless Ad Hoc Networks

Route caching strategy is important in on-demand routing protocols in wireless ad hoc networks. While high routing overhead usually has a significant performance impact in low bandwidth wireless networks, a good route caching strategy can reduce routing overheads by making use of the available route information more efficiently. In this paper, we first study the effects of two cache schemes, link cache and path cache, on the performance of on-demand routing protocols through simulations based on the Dynamic Source Routing (DSR) protocol. Since the path cache DSR has been extensively studied, we focus in this paper on the link cache DSR in combination with timer-based stale link expiry mechanisms. The effects of different link lifetime values on the performance of routing protocol in terms of routing overhead, packet delivery ratio and packet latency are investigated. A caching strategy incorporating adaptive link timeout is then proposed, which aims at tracking the optimal link lifetime under various node mobility levels by adaptively adjusting the link lifetime based on the real link lifetime statistics. The performance of the proposed strategy is then compared with the conventional path cache DSR. The results show that without a timeout mechanism, a link cache scheme may suffer severe performance degradation due to the use of broken routes, while the proposed adaptive link cache strategy achieves significantly improved performance by reducing the routing overhead when the network traffic load is high.     

The Complex Bootstrap Algorithm for Blind Separation of QAM Multiuser CDMA Signals

The bootstrap separator for multiuser signals is principally composed of cancelers, each one using the output of the other cancelers to facilitate control of its adaptive weight. In fact, such a structure performs as a signal separator rather than an interference canceler. Since for its separation there is no need for a reference signal (as in LMS cancelers), it is sometimes justifiably called a Blind Separator. However, for its operation the bootstrap separator requires a signal distinguisher termed discriminator. The algorithm was used in the past in applications such as dually polarized satellite communications and microwave terrestrial links. It was particularly reported for multiuser CDMA signal separating, with the signum function as discriminator. Especially for QAM signals, complex presentation is important. Therefore, we will concentrate in this report on what we call the Complex Bootstrap Algorithm. It is an extension to the previously reported bootstrap structure of [5]. We will examine its performance and emphasize the hardware saving in its implementation, and the ease of using it in simulation.     

Biasing a differential pair in low-voltage analog circuits: a systematic approach

This paper deals with a systematic approach to the common mode and the differential mode biasing of a differential transistor pair. Four different variants will be shown, two of these variants show practical importance; a practical circuit of one of these variants turns out to be the traditional long-tailed pair. This variant is mainly suited, if the input signal operates at voltage level, whereas another variant has great advantages if operation at current level occurs. Besides, the latter variant turns out to be very favorable in circuits operating with a single low supply voltage. Two practical circuits based on this variant are given.     

Design of High-Performance Wavelets for Image Coding Using a Perceptual Time Domain Criterion

This paper presents a new biorthogonal linear-phase wavelet design for image compression. Instead of calculating the prototype filters as spectral factors of a half-band filter, the design is based on the direct optimization of the lowpass analysis filter using an objective function directly related to a perceptual criterion for image compression. This function is defined as the product of the theoretical coding gain and an index called the peak-to-peak ratio, which was shown to have high correlation with perceptual quality. A distinctive feature of the proposed technique is a procedure by which, given a good starting filter, good filters of longer lengths are generated. The results are excellent, showing a clear improvement in perceptual image quality. Also, we devised a criterion for constraining the coefficients of the filters in order to design wavelets with minimum ringing.     

A necessary and sufficient condition for right coprime factorization of nonlinear feedback systems

In this short note, we establish a simple, yet precise, necessary and sufficient condition for the right coprime factorization of a nonlinear feedback control system. As a consequence, we also obtain similar conditions for the stable right coprime factorizations of the nonlinear feedback control system.     

Performance Analysis of Bidding Policy for Competitive Network Providers

This paper proposes an optimum bidding policy in a competitive network provider's environment, where each network provider can bid for individual connection requests according to its own criteria. The proposed bidding policy is based on the concept of shadow price. In other words, each network provider bids only for connection requests with an expected profit exceeding its shadow price. Because such connection request brings profit in the long term, each network provider can maximize its long-term profit by adopting this bidding policy. In this paper, the optimum bidding policy for network providers is analyzed by means of the policy iteration method derived from the Markov decision theory. The economic efficiency of the bidding policy is evaluated using several numerical examples, in which each network provider adopts fixed pricing and state-dependent pricing, respectively. By adopting the bidding policy in both cases, each network provider can maximize its long-term profit while the total users' consumer surplus is slightly reduced.     

Characterization of subthreshold MOS mismatch in transistors for VLSI systems

MOS transistor mismatch is revisited in the context of subthreshold operation and VLSI systems. We report experimental measurements from large transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400µm²). These are fabricated at different production qualified facilities in 40-nm gate oxide,n-well andp-well, mask lithography processes. Within the small area of our test-strips (3 mm²), transistor mismatch can be classified into four categories: random variations, edge, striation, and gradient effects. The edge effect manifests itself as a dependence of the transistor current on its position with reference to the surrounding structures. Contrary to what was previously believed, edge effects extend beyond the outer most devices in the array. The striation effect exhibits itself as a position-dependent variation in transistor current following a sinusoidal oscillation in space of slowly varying frequency. The gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.     

Economics of “design for test” to remain competitive in the 90s

This article emphasizes the criticality of maximizing value adders and minimizing the costs of design for test (DFT) in order to remain competitive in ASIC manufacturing in the 90s.     

Perspectives on Analytical Modeling of Small Geometry MOSFETs in SPICE for Low Voltage/Low Power CMOS Circuit Design

The present state of the art in analytical MOSFET modeling for SPICE circuit simulation is reviewed, with emphasis on the circuit design usage of these models. It is noted that the model formulation represents an upper limit of what is possible from any type of model, but that good parameter extraction is required to most closely approach that limit. The individual model types presently in common use are examined, with discussion of the behavior of each model, its strengths and weaknesses, its applicability to certain types of circuits, and criteria that a circuit design consumer can employ to judge a model before using it for circuit design. Some related issues, such as node charge and gate capacitance modeling, charge conservation, and statistical simulation of process variations, are also evaluated. Finally, new trends, directions, and requirements of MOSFET modeling for circuit simulation are considered.     

Mobile ATM buffer capacity analysis

This paper extends a stochastic theory for buffer fill distribution for multiple on and off sources to a mobile environment. Queue fill distribution is described by a set of differential equations assuming sources alternate asynchronously between exponentially distributed periods in on and off states. This paper includes the probabilities that mobile sources have links to a given queue. The sources represent mobile user nodes, and the queue represents the capacity of a switch. This paper presents a method of analysis which uses mobile parameters such as speed, call rates per unit area, cell area, and call duration and determines queue fill distribution at the ATM cell level. The analytic results are compared with simulation results.This paper is partially funded by ARPA contract number J-FBI-94-223.The Mathematica code for this paper can be found on http://www.tisl.ukans.edu/sbush.     

Computational experience with an effective heuristic for some capacity expansion problems in local access networks

We present a heuristic for multiplexer location problems in local access networks. The effectiveness of the heuristic is demonstrated on several real-life problem instances.Partially funded by an NSF PYI award, a consulting agreement with Bellcore, and an equipment grant from IBM.     

The significance of finite buffer edge effects in histogram measurements of queues

The empirically oberved fractal or self-similar nature of packet traffic implies heavy tailed queue processes for such traffic. However, based on our simulation analysis using real network data as well as standard models, we have found that the actual losses sustained are remarkably lower than those suggested by the heavy tail distribution. This can be explained by an effect observed in the tail of the histogram of a finite buffer queue process, which we call tail-raising, which contains information pertinent to performance estimation. This effect is also responsible for a significant reduction in packet losses for finite buffer systems, than would be otherwise predicted by the buffer overflow probability for heavy-tailed queues. We define a new parameter X _B on the histogram of a queue process for a finite buffer system, to calculate the tail of the queue process based on the information available in the histogram on the finite buffer. We propose an estimator that approximates X _B , namely, X _min, which is measurable because of the tail-raising effect and has a robust measurement method. The proposed estimator shows promise as a good predictor for performance metrics of queueing systems. We propose an innovative packet loss ratio estimation technique which uses histogram measurements combined with a virtual buffer scheme to find and extrapolate the objective packet loss rate using a binning strategy for histogram measurement, namely, Symmetric Logarithmic Binning (SLB).     

Current Mode Circuit Implementations of PWL Functions

Current-mode techniques have been used to realize improved basic building blocks of elementary piecewise linear (PWL) functions. These alternative circuit implementations, used for synthesis of precision PWL transfer characteristics, are described and compared in performance. In this paper, two optional topologies of the PWL function building blocks are proposed, based on the regulated cascode current mirror, current sources, Schottky prebiased diodes, and improved CMOS class AB prebiased diodes. The comparison of DC and high frequency performances is based on HSPICE simulation results and shows very good DC accuracy and transient time response of the proposed building blocks.     

Microsystems Engineering: A Great Stride Forward in Microelectronics Technology

The development of new-generation technological and engineering concepts by the example of microsystems technology and microsystems engineering approaches is considered.     

A mean-value analysis of slotted-ring network models

In this paper, we analyse Stochastic Petri Net (SPN) models of slotted-ring networks. We show that a simple SPN model of a slotted-ring network, which exhibits a product-form solution, yields similar results to a more detailed SPN model that has to be analysed by numerical means. Furthermore, we demonstrate a Mean-Value Analysis (MVA) approach to calculate efficiently the results for the simple model. This MVA approach allows for the movement of groups of tokens (customers) rather than just individual customers, as traditional MVA schemes for queueing network models do. Also, the MVA allows for non-disjoint place invariants, whereas previous MVA schemes addressed disjoint place invariants only. From the MVAs, it can be concluded that slotted-rings have very attractive performance characteristics, even under overload conditions (there is no thrashing). Also, we found that the choice of the slot size is a key factor in calibrating slotted-ring systems for optimal performance. Having a fast and reasonably accurate means available to evaluate the performance of slotted-ring systems, such as our proposed MVA, eases this calibration task. The proposed MVA for the product-form SPN models should therefore be regarded as a quick engineering tool.     

Noise considerations for mixed‐signal RF IC transceivers

This paper discusses design tradeoffs for mixedsignal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multipath fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit nonlinearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design tradeoffs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixedsignal noise coupling and to model substrate noise effects are presented.     

On the Capacity of IEEE 802.11 DCF with Capture in Multipath-Faded Channels

In this paper, we estimated the influence of capture effect over the capacity of IEEE 802.11b DCF within a single picocell. The channel utilization is examined analytically by introducing two capture models based on Rayleigh-distributed envelopes of the captured and the interfering frames divided into two local-mean power classes. Simulations in a pure Rician-faded channel depict the conditions under which both Rayleigh-faded capture models can be used to accurately predict the peak network capacity. Unlike the RTS/CTS handshake access mode, Basic access mode is significantly sensitive to the capture ratio, i.e., the receiver design. The packet size threshold over which it is convenient to switch from Basic to RTS/CTS handshake access scheme is also sensitive to the capture effect.