共查询到19条相似文献,搜索用时 62 毫秒
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针对内建自测试移相器,提出了一种基于逻辑仿真移相器设计和改进的快速算法。只需对几阶LFSR(Linear Feedback Shift Register)进行2^n-1个周期仿真即可得到合适的移相选择矢量,由这些选择矢量构成值胞。该方法得到的移相器选择矢量清晰地反映了值胞的组成和分布情况,从而避免了对偶LFSR的多次前向、后向仿真,降低了移相器的设计时间。对比实验表明,该方法是有效的,并且其硬件电路实现具有更小的硬件开销。 相似文献
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随着集成电路技术的发展,可测性设计在电路设计中占有越来越重要的地位,内建自测试作为可测性设计的一种重要方法也越来越受到关注。文中首先介绍了内建自测试的实现原理,在此基础上以八位行波进位加法器为例,详细介绍了组合电路内建自测试的设计过程。采用自顶向下的设计方法对整个内建自测试电路进行模块划分,用VHDL语言对各个模块进行代码编写并在QuartusII软件环境下通过了综合仿真,结果表明此设计合理,对电路的测试快速有效。 相似文献
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在BIST(内建自测试)过程中,线性反馈移位寄存器作为测试矢量生成器,为保障故障覆盖率,会产生很长的测试矢量,从而消耗了大量功耗.在分析BIST结构和功耗模型的基础上,针对test-per-scan和test-per-clock两大BIST类型,介绍了几种基于LFSR(线性反馈移位寄存器)优化的低功耗BIST测试方法,设计和改进可测性设计电路,研究合理的测试策略和测试矢量生成技术,实现测试低功耗要求. 相似文献
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在BIST(内建自测试)过程中,线性反馈移位寄存器作为测试矢量生成器,为保障故障覆盖率,会产生很长的测试矢量,从而消耗了大量功耗。在分析BIST结构和功耗模型的基础上,针对test-per-scan和test-per-clock两大BIST类型,介绍了几种基于LFSR(线性反馈移位寄存器)优化的低功耗BIST测试方法,设计和改进可测性设计电路,研究合理的测试策略和测试矢量生成技术,实现测试低功耗要求。 相似文献
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一种低功耗BIST测试产生器方案 总被引:7,自引:4,他引:3
低功耗设计呼唤低功耗的测试策略。文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的内建自测试测试产生器方案,该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑,对LFSR的输出和时钟进行调整,从而得到了准单输入跳变的测试向量集,使得待测电路的平均功耗大大降低,给出了以ISCAS'85/89部分基准电路为对象的实验结果,电路的平均测试功耗降幅在54.4%-98.0%之间,证明了该方案的有效性。 相似文献
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基于Walsh-Hadamard变换的扰码重建算法在最大成立数准则下寻找全局最优解,是求解线性反馈关系的一种有效方法,但其计算复杂度随着变换阶数的增加而迅速增加。为降低算法的计算复杂度,论文提出一种基于实时检测的扰码重建算法,即在进行Walsh-Hadamard变换的过程中,实时判断检测对象是否为反馈关系;当检测到反馈关系时,即可停止运算。引入实时检测后可使计算复杂度平均减少50%。 相似文献
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A fully scanned digital circuit can be tested pseudo-exhaustively by first introducing a number of extra bypass storage cells to limit the test-phase input dependency of each test-phase output and then using a Linear Feedback Shift Register (LFSR) to feed the chain of the original scan cells and the extra cells. For the design of the LFSR, the goal is to minimize the pseudo-exhaustive test length with low hardware overhead. If the LFSR uses a primitive characteristic polynomial then it requires only one seed, but the candidate primitive polynomials may all fail to satisfy the target test length. In this paper, we present a methodology that enlarges the list of candidate polynomials, if the prescribed number of seeds is more than one. Experimental results show that the new candidate polynomials are often instrumental in satisfying the given test length and seed restriction. 相似文献
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This paper presents a low-cost test technique using a new RF Built-In Self-Test (BIST) circuit for 4.5-5.5 GHz low noise amplifiers (LNAs). The test technique measures input impedance, voltage gain, noise figure, input return loss and output signal-to-noise ratio of the LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The BIST circuit contains test amplifier and RF peak detectors. The complete measurement set-up contains LNA with BIST circuit, external RF source, RF relays, 50 Ω load impedance, and a DC voltmeter. The test technique utilizes output DC voltage measurements and these measured values are translated to the LNA specifications such as input impedance and gain through the developed equations. The technique is simple and inexpensive. 相似文献
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具体研究on-Chip SRAM的内建自测试及其算法.在引入嵌入式存储器内建自测试的基础上,详细分析on-Chip SRAM内建自测试的具体实现方法,反映出内建自测试对于简化测试程序和缩短测试时间,从而降低测试成本的重要性.详细描述在测试on-Chip SRAM时常用的算法,并具体分析非传统性测试算法——Hammer算法和Retention算法. 相似文献
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This paper proposes a Built-In Self-Test (BIST) structure for measuring the gain and the 1-dB compression point of the Power Amplifier (PA) in transceiver ICs. In this structure, it is not necessary to use the external devices for mapping and DC measuring because of linearity of blocks, comparative performance in the linear region and the digital representation of the 1-dB compression point and gain value. The BIST Circuit is designed and simulated in 180 nm RF-CMOS process with Spectre-RF for a 900 MHz PA while it can achieve an acceptable accuracy which the input referred 1-dB compression point and gain value can be obtained with an error of about 0.2 dBm and 0.18 dB, respectively and the testing time is about 25 µs depends on resolution. Finally, in order to verify the proposed approach, we implemented practically a similar discrete circuit as proof-of-concept prototype that it obtained input referred 1-dB compression point value with an error of about 0.15 dBm. 相似文献
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Among test techniques for analog circuits, DC test is one of the simplest method for BIST application since easy to integrate test pattern generator and response analyzer are conceivable. Precisely, this paper presents such an investigation for a CMOS operational amplifier that is latter extended to active analog filters. Since the computation of fault coverage is still a controversy question for analog cells, we develop first an evaluation technique for optimizing the tolerance band of the measurements to test. Then, using some DFT solutions we derive single DC pattern and discuss the minimal number of points to test for the detection of defects. A response analyzer is integrated with a Built-in Voltage Sensor (BIVS) and provides directly a logic pass/fail test result. Finally, the extra circuitry introduced by this BIST technique for analog modules does not exceed 5% of the total silicon area of the circuit under test and detects most of the faults. 相似文献