Monitoring hot-carrier degradation in SOI MOSFETs by hot-carrierluminescence techniques

This paper addresses the problem of hot-carrier degradation and lifetime monitoring in SOI MOSFETs by means of hot-carrier-induced luminescence measurements. The peculiar emission behavior of SOI devices is clarified over a broad range of bias conditions by means of comparison with that of BULK MOSFETs. It is shown that detailed analysis of hot-carrier luminescence measurements at different photon energies provides a noninvasive monitoring tool for various aspects of degradation, such as worst case bias conditions, threshold voltage shift, and variations of the electric field and hot-carrier population in the damaged region. The measured light intensity represents also a sensitive acceleration factor for the extrapolation of lifetimes to real operating conditions     

A method for the prediction of hot-carrier lifetime in floating SOINMOSFETs

A concept was presented for the prediction of the device lifetimes for the hot-carrier effect (hot-carrier lifetimes) in floating SOI MOSFETs. The concept is that hot-carrier lifetimes in floating SOI MOSFETs can be predicted by estimating the hole current. In order to verify the validity of this concept, the hole current was investigated using device simulation. The results showed that the ratio of the hole current to the drain current in a floating-body SOI MOSFET is approximately equal to the ratio of substrate current to drain current in a body-tied one. Based on this fact, a method for accurately predicting the hot-carrier lifetime in floating-body SOI MOSFETs was proposed. The hot-carrier lifetime predicted with this method agreed well with the experimental results. This study showed that only the drain current difference between floating and body-tied structures results in lifetime differences, and there is no special effect on hot-carrier degradation in floating SOI MOSFETs. In this prediction, therefore, floating SOI MOSFETs can be treated in the same way as bulk MOSFETs. Hot-carrier lifetimes in floating SOI MOSFETs can be predicted using the hole current, while substrate currents are used in bulk MOSFETs     

Hot-electron-induced photon energies in n-channel MOSFETs operatingat 77 and 300 K

A detailed experimental study of the spectral distribution of hot-electron-induced photon emission in n-channel MOSFETs is presented. The study significantly improves on previous work by considering energies up to 3.1 eV and different operating temperatures. It is shown that in contrast with previous results, the photon energy distribution is markedly non-Maxwellian, thus suggesting that the same is true for the energy distribution of the channel electrons     

A test structure for spectrum analysis of hot-carrier-induced photoemission from MOSFETs

Hot-carrier-induced photoemission of subquarter-micron n-MOSFETs is analyzed using a specially designed test structure, which has a wide channel width of 2.0 mm for sufficient photoemission intensity. Since the test structure consists of parallel-connected unit MOSFETs and photoemission images are uniform, it can be estimated that the measured spectra are the same as those from unit MOSFETs. The relation between photon counts and photon energy suggests that photon energy has a Boltzmann distribution, exp(-h/spl nu//kT/sub e/). The electron temperature T/sub e/ calculated from the photon emission spectrum takes a minimum value at the channel length of 0.23 /spl mu/m. If T/sub e/ is related to device reliability, it suggests the possibility that the device structure optimized for a certain channel length may not be optimum for other channel length devices.     

Modeling of drain current overshoot and recombination lifetimeextraction in floating-body submicron SOI MOSFETs

This work reports on a new general modeling of recombination-based mechanisms related to electrically floating-body partially-depleted (PD) SOI MOSFETs. The model describes drain current overshoots induced when turning on the transistor gate and suggests a novel extraction method for the recombination lifetime in the silicon film. We show that the recombination process associated with drain current overshoots in PD silicon-on-insulator (SOI) MOSFETs takes place mainly in the depletion region and not in the neutral region as in case of pulsed MOS capacitors. Associated with existing techniques for generation lifetime extraction, our model offers, for the first time, the possibility of complete and rapid characterization for both generation and recombination lifetime using drain current transients in floating-body SOI MOSFETs. The model is used in order to characterize submicron SOI devices, allowing a thorough investigation of technological parameters impact on floating-body-induced transient mechanisms     

Monitoring hot-electron-induced degradation of floating-body SOIMOSFETs

A simple model relating the hot-electron-controlled device lifetime of floating-body SOI MOSFETs to the body voltage is discussed. The model is derived from the familiar relationship between the device lifetime and the substrate current of bulk MOSFETs, a relationship that cannot be measured directly in floating-body MOSFETs. The model, which allows quick estimation of the device lifetime from body-voltage measurements, is supported by measurements of hot-electron-induced degradation of floating-body SOI MOSFETs fabricated using SIMOX substrates     

利用激光器产生单模亚泊松光

对利用激光器产生单模亚泊松光进行了研究。提出了一个普遍的主方程,它适用于任意稳定的原子注入方式,并在该方程中,考虑了有限腔寿命的作用。得出了输出光子数的Mandel因子,并指出在泵噪声抑制的基础上通过减少腔寿命,可以代替抑制自发辐射,使输出光子数的涨落进一步减小。     

Evaluation technology of VLSI reliability using hot carrierluminescence

An evaluation technology for VLSI reliability using hot carrier luminescence has been developed. Problems with conventional electrical methods have been solved by the analysis of weak luminescence emitted from operating devices. Two applications are described. First, for the gate oxide evaluation, it is found that the best stress condition is determined by monitoring uniform photon count distribution emitted from the gate capacitors. Second, a method is proposed to find the weakest transistor in an LSI circuit against hot-carrier-induced degradation by counting photon emissions. This method is applied to the analysis of SRAMs (static RAMs) when the transistors to be improved have been detected     

A simple technique to measure generation lifetime in partiallydepleted SOI MOSFETs

This work presents a new, simple method of measuring the generation lifetime in silicon-on-insulator (SOI) MOSFETs. Lifetime is extracted from the transient characteristics of MOSFET subthreshold current. Using this technique, generation lifetime was mapped across finished SIMOX (Separation by IMplantation of OXygen) wafers and BESOI (Bonded and Etchedback SOI) wafers. BESOI material evaluated in this study had about seven times longer effective generation lifetime than SIMOX material and both the SIMOX and the BESOI are shown to have a lifetime variation of ±10% across four inch wafers     

Modeling and Probing Hot-Carrier Luminescence From MOSFETs

We present an extended modeling for MOSFETs that time-dependently predicts the spontaneous photon emission due to hot carriers. Such very faint luminescence waveforms (less than one photon for every 10⁶ switching events) can be measured by means of high-sensitivity single-photon detectors, where time jitter is lower than 30 ps. Thanks to the model, which runs in most computer-aided-design circuital simulators, it is possible to cross-check measurements with simulations in order to quickly identify either design and fabrication errors or mismatches due to parasitism, interconnections, etc. Moreover, we demonstrate that the proposed modeling is a powerful investigation tool not only for digital circuits but also for analog ICs.     

Experimental verification of the mechanism of hot-carrier-inducedphoton emission in n-MOSFETs using an overlapping CCD gatestructure

Experimental data are presented to verify the physical mechanism of hot-carrier-induced photon emission in n-MOSFETs. Using MOSFETs with an overlapping CCD gate structure, the multiple gates are biased to create hot-electron populations either at the drain junction or at the interelectrode gap regions. The results show that the magnitudes of the photon-generated minority carriers collected were comparable for hot-carrier-induced photons emitted from the drain junction and from the interelectrode gap regions, although the density of oppositely charged Coulomb centers (i.e. ionized drain dopants) available for bremsstrahlung in the interelectrode gap region is zero. These results show unambiguously that, for above-bandgap low-energy photons, bremsstrahlung of hot electrons in the Coulomb field of oppositely charged centers is not the dominant mechanism responsible for hot-carrier-induced photon emission in n-MOSFETs     

A microprogrammable real-time video signal processor (VSP) formotion compensation

A video signal processor (VSP) LSI circuit with a three pipelined architecture has been developed for pattern matching, which is fundamental for the motion compensation necessary for teleconferencing systems. A high-speed arithmetic logic unit with absolute-value calculation capability and a minimum/maximum value detector, which are essential to pattern matching, have been integrated on the VSP LSI. The chip was fabricated with a 2.5-μm CMOS and double-layer metallization technology. The number of MOSFETs integrated on the 9.91×9.50-mm ² chip is about 48000. It operates at a 14.3-MHz clock frequency with a single 5-V power supply and typically consumes 240 mW. An experimental video signal processing system, using a single VSP LSI chip, is discussed     

Local damage free Si substrate ultra thinning for backside emission spectral analysis using OBPF for LSI failure mode detection

In this study, we focused on an emission spectral analysis using OBPF, since emission spectral analysis is possible even with weak emissions. We also developed Si substrate local damage free thinning by ablation laser processing, and alkali solution wet etching for Si backside emission spectral analysis. The emission spectral analysis using an OBPF was effective for estimating the LSI semiconductor device failure mode and was able to classify the three failure modes of: gate oxide thin film leakage, P-N junction leakage and nMOSFET saturation current (Idsat) where gate floating occurs. Furthermore, we were able to estimate the failure mode, including metal/metal line short mode, from power approximation formula: Y = aX^b of a photon count increase rate by rising applied voltage at a PEMs observation. Each failure mode has it’s own coefficient “b” value. These two techniques allow a much more precise estimation of the representative failure mode of LSI semiconductor devices. Next, we developed damage free and large area local Si substrate thinning for backside emission spectral analysis at an isolated point. This technique uses a 266 nm DUV pulse laser ablation process and Si substrate crystal anisotrophic wet etching by KOH alkali solution. We achieved a damage free thinning area of approximately 2.6 × 2.6 mm². In addition, we developed a very precise, nondestructive calculation method for Si substrate with thickness of less than 2.3 μm by combining the interference fringe of equal thickness with an optical microscope, and an SEM image from depth of primary electron penetrations. The emission spectral analysis using OBPF from Si substrate backside became possible as an addition to surface analysis by combining thinning techniques with thickness calculations. We succeeded in estimating the failure mode by backside emission spectral analysis using these techniques.     

On the spontaneous lifetime change in an ideal planarmicrocavity-transition from a mode continuum to quantized modes

The spontaneous emission lifetime of an atom is known to be influenced by its environment. In general, the lifetime will be different if the atom is suspended in free space than if it is placed inside a cavity. A simple cavity geometry in which to explore this effect is the planar cavity. In a paper by Brorson, Yokoyama, and Ippen, the authors derived the minimum lifetime in a planar cavity to be one-third of the free space (no cavity) lifetime, and the appropriate mirror spacing was found to be one-half wavelength. In a paper by Yamamoto, Machida, and Bjork, it was concluded that the lifetime for a half-wavelength-long cavity was only two-thirds of the free space lifetime. In this paper, the discrepancy between these results is clarified and it is shown that the shortest lifetime is indeed one-third of the free space lifetime; but to achieve this, the cavity has to be slightly longer than one-half wavelength. This will influence the emission mode pattern in a way that, in general, is undesirable for a surface emitting laser. It is also shown that a strictly half-wavelength-long cavity has a lifetime of two-thirds of the free space lifetime. The model employed has the attractive feature that if allows a smooth transition from a fully open system with the atom interacting with a mode continuum, to the fully closed system with quantized photon modes     

超薄栅n-MOSFETs热载流子寿命预测模型

对氧化层厚度为 4和 5 nm的 n- MOSFETs进行了沟道热载流子应力加速寿命实验 ,研究了饱和漏电流在热载流子应力下的退化 .在饱和漏电流退化特性的基础上提出了电子流量模型 ,此模型适用于氧化层厚度为 4— 5 nm或更薄的器件     

Enhanced substrate current in SOI MOSFETs

This letter reports an enhanced substrate current at high gate bias in SOI MOSFETs. A comparison between coprocessed bulk and partially depleted SOI MOSFETs is used to present the enhancement unique to SOI devices and demonstrate the underlying mechanism. Other than electric field, a new source for carrier heating in the channel, i.e., self-lattice heating, is found to be responsible for the excess substrate current observed. The impact of this phenomenon on SOI device lifetime prediction and compact modeling under dynamic operating conditions typical of digital circuit operation is described. This SOI-specific enhancement must be considered in one-to-one comparisons between bulk and SOI MOSFETs regarding hot-carrier effects     

Converter-level FEM simulation for lifetime prediction of an LED driver with improved thermal modelling

Light-emitting diode (LED) drivers are widely regarded as the weakest link in the solid-state lighting systems. This paper proposes an improved thermal modelling process for the mission profile based lifetime prediction of reliability critical components in a LED driver for the outdoor lighting application. A converter-level finite element simulation (FEM) simulation is carried out to obtain the ambient temperature of electrolytic capacitors and power MOSFETs used in the LED driver, which takes into account the impact of the driver enclosure and the thermal coupling among different components. Therefore, the proposed method bridges the link between the global ambient temperature profile outside of the enclosure and the local ambient temperature profiles of the components of interest inside the driver. A quantitative comparison of the estimated annual lifetime consumptions of MOSFETs and capacitors are given based on the proposed thermal modelling process, and the datasheet thermal impedance models and the global ambient temperature.     

A 2×2 analog memory implemented with a special layoutinjector

Using floating gate MOSFETs, we have designed a 2×2 analog memory, which is expandable to any size array. The reduced programming voltage due to the innovative floating gate MOSFETs enables us to construct the analog memory with a standard double poly n-well process. In addition, a novel programming algorithm is presented. This method will contribute not only to a reduced total programming time, but also to a prolonged lifetime of the memory. The high voltage program/erase pulses are arranged to minimize the disturbance of nonselected cells. The resolution of a memory cell has been found to be 10 mV over a range of 1.25 V to 2 V which is equivalent to the information content of 6 digital cells     

CMOS technology-year 2010 and beyond

MOS large-scale-integration circuits (LSIs), having advanced remarkably during the past 25 years, are expected to continue to progress well into the next century. The progress has been driven by the downsizing of the components in an LSI, such as MOSFETs. However, even before the downsizing of MOSFETs reaches its fundamental limit, the downsizing is expected to encounter severe technological and economic problems at the beginning of next century when the minimum feature size of LSIs is going to shift to 0.1 and sub-0.1 μm. In this paper, the anticipated difficulties and some concepts for 0.1- and sub-0.1 μm LSIs are explained based on the research of the downsizing MOSFET into such a dimension, and a further concept for deep sub-0.1-μm LSIs is described     

Laser THz emission microscope as a novel tool for LSI failure analysis

We have proposed and developed a novel technique for a non-contact inspection of defective interconnections in an LSI chip using a laser terahertz emission microscope (LTEM). The LTEM measures the THz emission images of an LSI chip by scanning it with fs laser pulses. When a fs laser pulse irradiates a p–n junction in an LSI chip, transient photocurrent flows into interconnections resulting in the emission of the THz pulse into free space. We investigated the characteristics of the THz emissions from simple test element group samples which consist of p–n junctions connected to metal lines. It was found that the metallic lines connected to photo-excited p–n junctions worked as THz emission antennae which enhance the emission efficiency of THz pulses near their resonant frequencies corresponding to the line lengths. This result indicates that THz emission signals from p–n junctions in circuits strongly depend on the structure of the interconnections. We show the successful results on the inspection of defective interconnections in MOSFET devices and C7552 ISCAS’85 benchmark circuits using LTEM. By comparing the THz emission images between a normal circuit and a defective one, it is possible to identify the p–n junctions connected to the defective interconnections without electrical contacts.