Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

ALD of LaHfOx nano-laminates for high-κ gate dielectric applications

Electrical properties and thermal stability of LaHfO_x nano-laminate films deposited on Si substrates by atomic layer deposition (ALD) have been investigated for future high-κ gate dielectric applications. A novel La precursor, tris(N,N′-diisopropylformamidinato) lanthanum [La(ⁱPrfAMD)₃], was employed in conjunction with conventional tetrakis-(ethylmethyl)amido Hf (TEMA Hf) and water (H₂O). The capacitance-voltage curves of the metal oxide semiconductor capacitors (MOSCAPs) showed negligible hysteresis and frequency dispersion, indicating minimal deterioration of the interface and bulk properties. A systematic shift in the flat-band voltage (V_fb) was observed with respect to the change in structure of nano-laminate stacks as well as La₂O₃ to HfO₂ content in the films. The EOTs obtained were in the range of ∼1.23-1.5 nm with leakage current densities of ∼1.3 × 10⁻⁸ A/cm² to 1.3 × 10⁻⁵ A/cm² at V_fb − 1 V. In addition, the films with a higher content of La₂O₃ remained amorphous up to 950 °C indicating very good thermal stability, whereas the HfO₂ rich films crystallized at lower temperatures.     

Influence of rapid thermal annealing temperature on structure and electrical properties of high permittivity HfTiO thin film used in MOSFET

HfTiO thin films were prepared by r.f. magnetron co-sputtering on Si substrate. To improve the electrical properties, HfTiO thin films were post heated by rapid thermal annealing (RTA) at 400 °C, 500 °C, 600 °C and 700 °C in nitrogen. It was found that the film is amorphous below 700 °C and at 700 °C monoclinic phase HfO₂ has occurred. With the increase of the annealing temperature, the film becomes denser and the refractive index increases. By electrical measurements, we found at 500 °C annealed condition, the film has the best electrical property with the largest dielectric constant of 44.0 and the lowest leakage current of 1.81 × 10⁻⁷ A/cm², which mainly corresponds to the improved microstructure of HfTiO thin film. Using the film annealed at 500 °C as the replacement of SiO₂ dielectric layer in MOSFET, combining with TiAlN metal electrode, a 10 μm gate-length MOSFET fabricated by three-step photolithography processes. From the transfer (I_DS–V_G) and output (I_DS–V_DS) characteristics, it shows a good transistor performance with a threshold voltage (V_th) of 1.6 V, a maximum drain current (I_ds) of 9 × 10⁻⁴ A, and a maximum transconductance (G_m) of 2.2 × 10⁻⁵ S.     

Electrical characterization and morphological properties of AlN films prepared by dc reactive magnetron sputtering

Aluminum nitride (AlN) films were deposited by dc reactive magnetron sputtering on p-Si-(1 0 0) substrate in Ar-N₂ gas mixtures. The effects of nitrogen concentration and sputtering power on AlN films deposition rate, crystallographic orientation, refractive index, and surface morphology are investigated by means of several characterization techniques. The results show that AlN films reasonably textured in (0 0 2) orientation with low surface roughness can be obtained with the deposition rate as high as 70 nm/min by the control of either target power or N₂ concentration in the gas mixture. Increasing the dc discharge power, Al atoms are not completely nitridized and the Al phases appear, as well as the AlN phases. MIS (Metal-Insulator-Semiconductor) structures were fabricated and electrically evaluated by I-V (current-voltage) and C-V (capacitance-voltage) measurements at high frequency (1 MHz). The results obtained from C-V curves indicate that charges at the dielectric/semiconductor interface occur, and the dielectric constant values (extracted under strong accumulation region) are compatible with those found in literature.     

Water-soluble poly(3,4-ethylenedioxythiophene)/nano-crystalline TiO2 heterojunction solar cells

Nanocrystalline titanium dioxide (TiO₂) thin films were prepared by the sol-gel method and were then used to fabricate an indium-tin oxide (ITO)/nano-crystalline TiO₂/poly(3,4-ethylenedioxythiophene) (PEDOT)/Au device. The junction thus obtained shows a rectifying behavior. Their current-voltage (I-V) characteristics in dark indicate that a heterojunction at the nano-crystalline TiO₂/PEDOT interface has been created. The measured open-circuit voltage (V_oc) and short-circuit current (I_sc) for the device under illumination with 50 mW/cm² light intensity under AM 1.5 conditions (device dimension was 1 cm²) are V_oc=0.39 V, I_sc=54.9 μA/cm², the filling factor (FF)=0.429 and the energy conversion efficiency (η)=0.03%.     

Resistive switching characteristics of ultra-thin TiOx

We investigated the resistive switching characteristics of Ir/TiO_x/TiN structure with 50 nm active area. We successfully formed ultra-thin (4 nm) TiO_x active layer using oxidation process of TiN BE, which was confirmed by X-ray Photoelectron Spectroscopy (XPS) depth profiling. Compared to large area device (50 μm), which shows only ohmic behavior, 250 and 50 nm devices show very stable resistive switching characteristics. Due to the formation and rupture of oxygen vacancies induced conductive filament at Ir and TiO_x interface, bipolar resistive switching was occurred. We obtained excellent switching endurance up to 10⁶ times with 100 ns pulse and negligible degradation of each resistance state at 85 °C up to 10⁴ s.     

High performance TaYOx-based MIM capacitors

TaYO_x-based metal-insulator-metal (MIM) capacitors with excellent electrical properties have been fabricated. Ultra-thin TaYO_x films in the thickness range of 15-30 nm (EOT ∼ 2.4-4.7 nm) were deposited on Au/SiO₂ (100 nm)/Si (100) structures by rf-magnetron co-sputtering of Ta₂O₅ and Y₂O₃ targets. TaYO_x layers were characterized by X-ray photoelectron spectroscopy (XPS), energy dispersive X-ray (EDX) and X-ray diffraction (XRD) to examine the composition and crystallinity. An atomic percentage of Ta:Y = 58.32:41.67 was confirmed from the EDX analysis while XRD revealed an amorphous phase (up to 500 °C) during rapid thermal annealing. Besides, a high capacitance density of ∼3.7-5.4 fF/μm² at 10 kHz (ε_r ∼ 21), a low value of VCC (voltage coefficients of capacitance, α and β) have been achieved. Also, a highly stable temperature coefficient of capacitance, TCC has been obtained. Capacitance degradation phenomena in TaYO_x-based MIM capacitors under constant current stressing (CCS at 20 nA) have been studied. It is observed that degradation depends strongly on the dielectric thickness and a dielectric breakdown voltage of 3-5 MV/cm was found for TaYO_x films. The maximum energy storage density was estimated to be ∼5.69 J/cm³. Post deposition annealing (PDA) in O₂ ambient at 400 °C has been performed and further improvement in device reliability and electrical performances has been achieved.     

Electrical characterisation of SiON/n-Si structures for MOS VLSI electronics

In the present work, we examine the properties of SiON films grown on Si substrates by CVD in order to investigate their suitability as potential materials in replacing SiO₂ in metal-oxide-semiconductor (MOS) devices. Suitable metallization created MOS devices and electrical characterisation took place in order to identify their electrical properties. Electrical measurements included current-voltage (I-V), capacitance-conductance-voltage (C-V) measurements and admittance spectroscopy (Y−ω) allowing determination of the bulk charges and the dielectric response of the films. The analysis of the data also took into account the presence of traps at the Si/SiON interface calculated by a fast conductance technique. The interface states density was of the order of 10¹² eV⁻¹ cm⁻². The dielectric constant was found to lie between 16 and 4.5 and the corresponding bulk trapped charges were found between 8 and 113 μCb cm⁻². Post deposition annealing altered these values showing an improvement of the device behaviour. A short explanation of the above is also provided.     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.     

Circuital modelling of S-shape removal in the current–voltage characteristic of TiOx inverted organic solar cells through white-light soaking

In this work light activation phenomenon in inverted bulk heterojunction (BHJ) organic solar cells (OSC) has been electrically modelled with a two-diode equivalent circuit. OSC are based on poly(3-hexylthiophene) (P3HT): 1-(3-methoxycarbonyl)-propyl-1-1-phenyl-(6,6) C61 (PCBM) with a titanium oxide (TiO_x) sublayer. Current–voltage (I–V) characteristics show a highly pronounced S-shape that is gradually removed during light activation process. The circuit used to model I–V curves includes two diodes in forward and reverse bias together with two parallel resistances, R_P1 and R_P2. The parallel of the reverse bias diode and its corresponding resistance R_P2 models the electrical behaviour of the TiO_x interlayer. This interlayer has been thermally treated at different temperatures, from 80 °C up to 180 °C, reducing the activation time from 400 s for unbaked devices down to 30 s for devices annealed at temperatures higher than 80 °C. The S-shape shown in the I–V characteristic is completely removed after a few minutes of white-light illumination. I–V curves recorded during the activation process have been fitted with the analytical solution of the two-diode circuit based on W-Lambert function. A decrease of the subcircuit 2 equivalent resistance has been found to be the cause of S-shape removal. This resistance diminishing is in good agreement with the increase of TiO_x conductance with baking temperature and white-light exposure time found by other authors.     

Ruthenium oxide metal nanocrystal capacitors with high-κ dielectric tunneling barriers for nanoscale nonvolatile memory device applications

The ruthenium oxide metal nanocrystals embedded in high-κ HfO₂/Al₂O₃ dielectric tunneling barriers prepared by atomic layer deposition in the n-Si/SiO₂/HfO₂/ruthenium oxide (RuO_x)/Al₂O₃/Pt memory capacitors with a small equivalent oxide thickness of 8.6 ± 0.5 nm have been investigated. The RuO_x metal nanocrystals in a memory capacitor structure observed by high-resolution transmission electron microscopy show a small average diameter of ∼7 nm with high-density of >1.0 × 10¹²/cm² and thickness of ∼3 nm. The ruthenium oxide nanocrystals composed with RuO₂ and RuO₃ elements are confirmed by X-ray photoelectron spectroscopy. The enhanced memory characteristics such as a large memory window of ΔV ≈ 12.2 V at a sweeping gate voltage of ±10 V and ΔV ≈ 5.2 V at a small sweeping gate voltage of ±5 V, highly uniform and reproducible, a large electron (or hole) storage density of ∼1 × 10¹³/cm², low charge loss of <7% (ΔV ≈ 4.2 V) after 1 × 10⁴ s of retention time are observed due to the formation of RuO_x nanocrystals after the annealing treatment and design of the memory structure. The charge storage in the RuO_x nanocrystals under a small voltage operation (∼5 V) is due to the modified Fowler-Nordheim tunneling mechanism. This memory structure can be useful for future nanoscale nonvolatile memory device applications.     

Study of gate dielectric permittivity variation with different equivalent oxide thickness on channel engineered deep sub-micrometer n-MOSFET device for mixed signal applications

The impact of high permittivity gate dielectrics with different equivalent oxide thickness (EOT) for conventional, low and high tilt angle halo implants on the performance of 100 nm n-MOSFETs device is studied using device simulator Synopsys ISE-TCAD. In this paper, we systematically increase the value of gate dielectric (3.9-50) and investigate its effects on conventional, low angle of tilt (10^o) and high angle of tilt (50^o) halo implants for different device parameters of 100 nm n-MOSFETs using two different EOT viz. 1.5 nm and 2.0 nm. The impact of gate dielectric permittivity along with the different angles of halo implants on short channel performance contributing to the DIBL, the subthreshold swing, I_ON/I_OFF ratio, and the threshold voltage V_T are studied for two different EOT thicknesses. The device has been investigated for digital performance parameters like the variation of substrate-body voltage on DIBL, I_OFF, I_ON and the threshold voltage V_T for sub 100 nm technology generation. It has also been investigated for analog performance like trans-conductance generation factor (gm/I_D) and overall gain (gmR₀).     

Annealing effect on the metal gate effective work function modulation for the Al/TiN/SiO2/p-Si structure

In this work, the thermal annealing effect on the metal gate effective work function (EWF) modulation for the Al/TiN/SiO₂/p-Si(1 0 0) structure was investigated. Compared with the sample of TiN/SiO₂/p-Si(1 0 0) structure, for the sample additionally capped with Al the flat band voltage has a very obvious shift as large as 0.54 V to the negative direction after forming gas annealing. It is also revealed that the thermal budget can effectively influence both the EWF of the gate electrode and the thickness of the gate dielectric layer when a post annealing at 600 °C with different soak times was applied to the samples with Al cap. Material characterization indicates that the diffusion of Al and the formation of Al oxide during annealing should be responsible for all the phenomena. The interface trap density Dit calculated from the high-frequency C-V and the laser-assisted high-frequency C-V curves show that the introduction of Al does not cause reliability problem in the Al/TiN/SiO₂/p-Si structure.     

Improvement on low-temperature deposited HfO2 film and interfacial layer by high-pressure oxygen treatment

In this study, high-pressure oxygen (O₂ and O₂ + UV light) technologies were employed to effectively improve the properties of low-temperature-deposited metal oxide dielectric films and interfacial layer. In this work, 13 nm HfO₂ thin films were deposited by sputtering method at room temperature. Then, the oxygen treatments with a high-pressure of 1500 psi at 150 °C were performed to replace the conventional high temperature annealing. According to the XPS analyses, integration area of the absorption peaks of O-Hf and O-Hf-Si bonding energies apparently raise and the quantity of oxygen in deposited thin films also increases from XPS measurement. In addition, the leakage current density of standard HfO₂ film after O₂ and O₂ + UV light treatments can be improved from 3.12 × 10⁻⁶ A/cm² to 6.27 × 10⁻⁷ and 1.3 × 10⁻⁸ A/cm² at |Vg| = 3 V. The proposed low-temperature and high pressure O₂ or O₂ + UV light treatment for improving high-k dielectric films is applicable for the future flexible electronics.     

Electrical properties of vacuum annealed La2O3 thin films grown by E-beam evaporation

In this article, the conduction mechanisms of metal-oxide-semiconductor with vacuum annealed Lanthana (La₂O₃) oxide film are investigated. Lanthana films with thicknesses of 3.5, 4.7, and 11 nm were deposited by E-beam evaporation on n-Si (100), and annealed at various temperatures (300-500 °C) in ultra-high vacuum (10⁻¹⁰-10⁻⁹ Torr) for 90 min. From the measurement of spectroscopic ellipsometry, it is found that film thickness is increased with annealing temperature, which would be cause of flat-band voltage shift (ΔV_FB) due to the growth of interfacial layer. From the capacitance measurement, it is found that ΔV_FB of the film is reduced by post-deposition anneal (PDA) compared to that of as-deposited film, but increase again at high temperature annealing, especially in the case of thin film (3.5 nm). From the applied voltage and temperature dependence of the leakage current of the film, with different gate electrode materials (Ag, Al, and Pt), it is shown that the leakage currents are associated with ohmic and Poole-Frenkel (P-F) conductions when flat-band voltage (V_FB) is less than zero, and ohmic and Space-Charge-Limited Current (SCLC) conductions when V_FB is greater than zero. The dielectric constants obtained from P-F conduction for Al gate electrode case is found to be 11.6, which is consistent with the C-V result 11.9. Barrier height of trap potential well is found to be 0.24 eV from P-F conduction. Based on SCLC theory, leakage currents of 3.5 and 11 nm films with different PDA temperatures are explained in terms of oxide trap density.     

The deposition of nanocrystalline TiO2 thin film on silicon using Sol-Gel technique and its characterization

TiO₂ thin films were deposited using Sol-Gel spin coating technique using titanium isoperoxide as the Titania precursor. The films were characterized using X-ray diffraction, capacitance voltage measurement and Raman characterization technique. The XRD and Raman spectra indicate the presence of anatase TiO₂ phase in the film. The grain size as calculated using the Scherrer’s formula was found to be 30, 66 and 59 nm for TiO₂(0 0 4), TiO₂(2 0 0) and TiO₂(2 1 1), respectively. The grain size was found to increase after annealing at 800 °C. The dielectric constant as calculated using capacitance voltage measurement was found to be 25. The refractive index of the film was 2.34.     

Electrical and reliability characteristics of GaAs MOSHEMTs utilizing high-k IIIB and IVB oxide layers

In this work, the high-k material of gadolinium oxide layer (Gd₂O₃) and zirconium oxide layer (ZrO₂) thin films were fabricated as the gate dielectric insulator materials in GaAs metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs). The dielectric constant of Gd₂O₃ and ZrO₂ oxide layers were estimated to be 10.6 and 7.3 by the MOS-ring capacitor of C-V measurements. In addition, the thermal stability of the devices have been investigated and compared with the high-k material Gd₂O₃ and ZrO₂ thin films for reliability tests. The Gd₂O₃ MOSHEMTs achieved a better thermally stable characteristic duo to its similar lattice structure with GaAs native oxide layer. At high temperature operation, the V_BR degradation slope was 1.2 × 10⁻³ V/°C and the maximum I_ds degradation slope was 1.4 × 10⁻² mA (%)/°C. According to this, the device also showed a good reliability characteristic within 48 h. Based on measurement results, the Gd₂O₃ MOSHEMTs exhibited the best electrical characteristics, including the lowest gate leakage current, the lowest noise spectra density, and the high power performance. Therefore, the Gd₂O₃ MOSHEMTs is suitable for high power amplifier and monolithic microwave integrated circuits (MMICs) applications.     

Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON

For the first time, we present a comparative study on HfLaSiON and HfLaON gate dielectric with an equivalent oxide thickness (EOT) of 0.8 nm (T_inv = 1.2 nm). A detailed DC analysis of I_on vs. I_off shows HfLaON performs somewhat better than HfLaSiON. However, positive bias temperature instability (PBTI) lifetime of HfLaSiON is higher than HfLaON by about 2 orders of magnitude. On the other hand, hot carrier stress lifetime for HfLaSiON was similar to that of HfLaON. From the activation energy and U-trap, we found that the cause of different threshold voltage (V_T) shifts under PBT stress and detrapping was originated from stable electron traps induced by different charge trapping rates.     

A diketopyrrolopyrrole containing molecular semiconductor: Synthesis,characterization and solution-processed 1D-microwire based electronic devices

Highly oriented 1D-microwires of a diketopyrrolopyrrole (DPP) based semiconductor i.e. DPP(CBZ)₂ (Carbazole capped DPP) were synthesized, characterized and applied to the fabrication of organic optoelectronic devices. 1D-microwires of DPP(CBZ)₂ were prepared by solution processing on capillary tubes serving to pin solution. A bottom-gate, top-contact field-effect transistor employing 1D-microwire and polymeric gate dielectric showed a hole mobility of 1.24 × 10⁻² cm²/V s, an on-to-off drain current ratio (I_on/I_off) of 4.7 × 10³ and subthreshold slopes of 4 V/dec under ambient conditions. Under white light, a photosensitivity of 800 at V_G = −40 V and photoresponsivity of 830 mW/A were achieved. This work demonstrates the potential of this new molecule and the solution method for use in various opto-electronic devices such transistors, photosensors and photovoltaics.     

Low gate interface traps AlGaN/GaN HEMTs using a lattice matched ZrZnO transparent gate design

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) using a radio-frequency magnetron sputtered ZrZnO transparent oxide layer as a gate insulator are investigated and compared with traditional GaN HEMTs. A negligible hysteresis voltage shift in the C–V curves is seen, from 0.09 V to 0.36 V, as the thickness of ZrZnO films increases. The composition of ZrZnO at different annealing temperatures is observed using X-ray photoelectron spectroscopy (XPS). The ZrZnO thin film achieves good thermal stability after 600 °C, 700 °C and 800 °C post-deposition annealing (PDA) because of its high binding energy. Based on the interface trap density analysis, D_it has a value of 2.663 × 10¹² cm⁻²/eV for 10-nm-thick ZrZnO-gate HEMTs and demonstrates better interlayer characteristics, which results in a better slopes for the I_ds degradation (5.75 × 10⁻¹ mA/mm K⁻¹) for operation from 77 K to 300 K. The 10-nm-thick ZrZnO-gate device also exhibits a flat and a stable 1/f noise, as V_GS–V_th, and at various operating temperatures. Therefore, ZrZnO has good potential for use as the transparent film for a gate insulator that improves the GaN-based FET threshold voltage and improves the number of surface defects at various operating temperatures.