Effects of fluoride residue on Cu agglomeration in Cu/low-k interconnects

We have investigated the effects of fluoride residue on the thermal stability of a Cu/barrier metal (BM)/porous low-k film (k < 2.3) structure. We confirmed that the Cu agglomerated more on a BM/inter layer dielectric (ILD) with a fluoride residue. To consider the effect of fluoride residue on Cu agglomeration, the structural state at the Cu/BM interface was evaluated with a cross-section transmission electron microscope (TEM) and atomic force microscope (AFM). And the chemical bonding state at the Cu/BM interface was evaluated with the interface peeling-off method and X-ray photoelectron spectroscopy (XPS). Moreover, we confirmed the oxidation of Cu with fluoride in accelerated conditions to clarify the effect of fluoride on Cu. Our experiments suggested that the fluoride residue led to the formation of a metal fluoride, and this accelerated the Cu agglomeration accompanying an increase in Cu oxidation.     

晶圆制造、运输、封装过程中Al焊垫污染源的研究

半导体芯片上Al键合焊垫在集成电路器件良率测试和封装中是非常重要的。研究焊垫污染来源对晶圆制造和金线键合工艺的改进将会有极大的帮助。结合案例采用扫描电子显微镜(SEM)、能量弥散X射线探测器(EDX)、透射电子显微镜(TEM)、聚焦离子束显微镜(FIB)等分析研究了焊垫污染的来源。结果表明,键合焊垫上的F沾污的来源可能与顶层金属蚀刻或焊垫打开过程中的蚀刻气体或者运输相关;异常焊垫上较高的C和O可能是在晶背减薄过程中引入的;运输过程中的包装纸导致了异常焊垫上O和K沾污;异常焊垫上的Si尘埃形成于晶粒切割过程中;焊垫腐蚀区域的Cl则来源于焊垫蚀刻气体。     

Band diagram for low-k/Cu interconnects: The starting point for understanding back-end-of-line (BEOL) electrical reliability

The starting point for describing the electrostatic operation of any semiconductor device begins with a band diagram illustrating changes in the semiconductor Fermi level and the alignment of the valence and conduction bands with other interfacing semiconductors, insulating dielectrics and metal contacts. Such diagrams are essential for understanding the behavior and reliability of any semiconductor device. For metal interconnects, the band alignment between the metal conductor and the insulating intermetal and interlayer dielectric (ILD) is equally important. However, relatively few investigations have been made. In this regard, we have investigated the band alignment at the most common interfaces present in traditional single and dual damascene low-k/Cu interconnect structures. We specifically report combined X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy (REELS) measurements of the Schottky barrier present at the ILD and dielectric Cu capping layer (CCL) interfaces with the Ta(N) via/trench Cu diffusion barrier. We also report similar measurements of the valence and conduction band offsets present at the interface between a-SiN(C):H dielectric CCLs and low-k a-SiOC:H ILDs (porous and non-porous). The combined results point to metal interfaces with the CCL having the lowest interfacial barrier for electron transport. As trap and defect states in low-k dielectrics are also important to understanding low-k/Cu interconnect reliability, we additionally present combined electron paramagnetic resonance (EPR) and electrically detected magnetic resonance (EDMR) measurements to determine the chemical identity and energy level of some electrically active trap/defect states in low-k dielectrics. Combined with the photoemission derived band diagrams, the EPR/EDMR measurements point to mid-gap carbon and silicon dangling bond defects in the low-k ILD and CCL, respectively, playing a role in electronic transport in these materials. We show that in many cases the combined band and defect state diagrams can explain and predict some of the observed reliability issues reported for low-k/Cu interconnects.     

表面光电压法研究氧化工艺铁离子沾污

表面光电压法(SPV)能精确测量硅片的Fe离子浓度,是一种快速、非破坏性的高灵敏度测试方法。采用表面光电压技术研究了氧化工艺中的Fe离子沾污。研究表明,氧气、氮气、三氯乙烯中含有的微量杂质是氧化工艺中Fe离子沾污的主要来源。通过对氧气、氮气进行进一步纯化处理、减少三氯乙烯杂质质量分数到1.0×10-8、更换传输气体的不锈钢管路等措施,将氧化工艺Fe离子沾污减少了一个数量级。     

Quantifying the impact of homogeneous metal contamination usingtest structure metrology and device modeling

Deposition of metallic impurities from HF process solutions has been investigated experimentally and explained theoretically in a qualitative manner. The depositions are shown to be electrochemical in nature in that an oxidation reduction reaction results in metal ions in solution depositing on the wafer as elements with an oxidation state of 0. The theory is only qualitative in that it can only predict which metals will deposit, not how much. Experimentally, simple transmission equations can be determined which relate metallic contamination levels on Si wafer surfaces (atoms/cm²) to metal concentration in the solution (ppb). Simple test structures have been fabricated with known amounts of iron and copper contamination in the pregate oxide clean of a 1.25 μm CMOS process. Device measurements indicate device degradation in the case of copper, confirming deposition studies that copper deposits from HF solutions. Iron contaminated wafers show no contamination related device effects, in support of theoretical predictions and deposition studies indicating iron does not deposit from HF solutions. The importance and potential usefulness of test structures as homogeneous contamination monitors is illustrated through device modeling of the contamination effects observed in the test structures that can then be used to estimate the effects of such contamination on ULSI circuit performance     

Surface treatment of wire bonding metal pads

The random formation of micrometric crystals on Al bonding pads can be an issue affecting wire bonding metal pad quality. The dry etch chemistry used to remove final passivation dielectric layers from the top of the bonding Al pad area is in fact based mainly on fluorine-containing gases (such as CF₄, CHF₃, etc.) which can leave fluorine as a residual on the metal pad surface as bonded or “free” AlF₃, especially in the metal grain boundary zones. Fluorine contamination on the Al wire bonding pads, under particular temperature and humidity conditions, causes the formation of Al(OH)₃ and Al/fluorine compound crystallites, not allowing, as a consequence, growth of the superficial and homogeneous natural Al₂O₃ layer. This paper concerns the analytical methods used to reveal the formation of such crystal defects and the operative solutions effective in preventing them, leaving the metal pad surface in the optimal condition for subsequent wire bonding operations.     

A gate-charging model for ILD related plasma processes in MOSFETs

A model explaining gate-charging damage in MOSFETs observed during inter-layer-dielectric (ILD)-related plasma processes is reported. It indicates that the charging damage associated with the ILD plasma process can be related to the effect of photoconduction and/or capacitive impedance coupling of plasma potential through the multiple ILD layers. The model leads to a conclusion that by placing a larger-area lower-layer metal (such as Metal-1) plate or polysilicon plate at the gate terminal of MOSFETs, this ILD process-related charging damage can be eliminated or significantly reduced due to a substantial reduction in the gate-to-substrate impedance of the transistors.     

Carrier Transportation Mechanism of the $hbox{TaN}/ hbox{HfO}_{2}/hbox{IL}/hbox{Si}$ Structure With Silicon Surface Fluorine Implantation

In this paper, the current transportation mechanism of HfO₂ gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO₂/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO₂ barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HfOF conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO₂ conduction band, which contributes to Frenkel-Poole conduction.     

The role of oxygen in electron cyclotron resonance etching of silicon carbide

The electron cyclotron resonance (ECR) etching of silicon carbide (SiC) was studied using SF₆ + O₂ based plasma. The role of O₂ was studied by varying the O₂ flow rate while keeping the total gas flow constant. It was found that oxygen enhances the etch rate at low O₂ fraction through releasing more fluorine atoms, while lowers the etch rate at high O₂ fraction by diluting fluorine atoms and forming an oxide-like layer. The etched surface roughness was found to be affected by the surface oxidation and oxygen ion related physical ion bombardment. The role of oxygen in chemical etching of carbon was found to be insignificant. In general, the etched surface is smooth and free of micromasking effect that can arise from Al contamination and C rich layer.     

V “Bridged” Co?O to Eliminate Charge Transfer Barriers and Drive Lattice Oxygen Oxidation during Water-Splitting

Oxygen evolution reaction (OER) and hydrogen evolution reaction (HER) play significant role on the practical applications of water splitting for producing clean fuel. Although some low-cost metal oxides are active on catalyzing OER and HER, the instinct drawback of sluggish charges carriers transfer mobility decrease the reactions kinetic and hinder their application. To overcome the issue, Co V oxide is successfully built-up with a Co O V structure to eliminate energy barrier during carriers transfer by the spin-flip hopping process, which can be coated on various substrate to stimulate OER and HER. Moreover, the V “bridge” between Co O bonds stimulates the OER through more effective lattice oxygen oxidation mechanism, which can directly format O O bond in more effective pathway. The protocol could be spread on rational design of such OER electrocatalysts on various electrode to lower-cost water splitting.     

An analytical model of multiple ILD thickness variation induced byinteraction of layout pattern and CMP process

In this paper, an analytical model for chemical mechanical polishing (CMP) is described. This model relates the physical parameters of the CMP process to the in-die variation of interlayer dielectric (ILD) in multilevel metal processes. The physical parameters considered in this model include the deposited ILD profile, deformation of the polishing pad and the hydrodynamic pressure of slurry flow. Model parameters are adjusted based on the first ILD layer and then applied to the upper ILD layers. Comparison of simulated results with sample data is performed at the die level of a state-of-the-art microprocessor     

微芯片铝键合点上氟沾污物成分的研究

微芯片铝键合系统的失效是器件可靠性研究的重要课题,铝键合点上的氟沾污加速了对铝合金化表面的腐蚀,导致微芯片的失效。国外的工作多数讨论氟沾污引起失效的机理;很少给出沾污物的系列化学成份。ＴＯＦ ＳＩＭＳ提供了一个探测和分析微芯片键合点上沾污成份的有力武器,作者比较了两个ＴＯＦ ＳＩＭＳ的负离子谱,一个是经目检发现键合点上有沾污斑点的芯片,另一个是键合点无沾污的芯片。根据对ＴＯＦ ＳＩＭＳ特征谱线和离子像的研究,认为沾污点的化学成份主要是铝氟化合物和铝氧氟化合物。进一步的工作发现除微芯片的制造工艺过程外,成品圆片的存放处理也是形成键合点上氟沾污的原因。     

Material modification of the patterned wafer during dry etching and strip determined by XPS

XPS analysis on single damascene (SD) patterned wafers was performed to study the modification of materials, especially the sidewall, during etching and strip. LKD-5109, MSQ-type materials (k≈2.2) were used as ILD, SiC/SiO₂ as top hard mask (HM), and SiC as bottom liner. The etching in Ar/CF₄/CH₂F₂/O₂ creates a CF_x polymer passivation layer on all patterned surfaces. The etched sidewall surface consists of two regions; a thin skin layer of CF_x polymer and CF-rich SiOC layer behind. An N₂/O₂ strip removes CF_x polymer and CF-rich layer efficiently (less than 1 at.% fluorine content). Instead of fluorine, CN-rich layers containing 11–20 at.% nitrogen were observed for all surfaces. After N₂/O₂ strip, the sidewall consists of two regions; a few nanometers of CN rich SiOC layer at the surface and several tens of nanometers of a C-depleted oxide type layer. N₂/H₂ strip provides a thinner C-depleting oxide type layer than either N₂/O₂ and CF₄/O₂ strips. However, the N₂/H₂ strip cannot eliminate fluorine contamination more than the N₂/O₂ strip.     

A Nondestructive Method of Extracting the Width and Thickness of Interconnects for a 40-nm Technology

In this paper, a simple and nondestructive method of modeling 40-nm interconnects is proposed. Traditional methods based on charge-based capacitance measurement model the interconnects by fitting the capacitance or resistance curves, first by assuming one constant process parameter, such as metal thickness, and then by extracting the metal width, metal spacing, and interlevel dielectric (ILD) thickness from certain test patterns that may therefore result in model inaccuracy while the transmission and scanning electron microscopy methods are both destructive and time consuming. The proposed new methodology directly extracts the metal width based on the metal resistance test structures, and then the metal thickness, metal spacing, and ILD thickness without any presumption. It is also nondestructive and fast, with a model accuracy higher than 95%. Furthermore, with the ensured accuracy of layout parameter extraction, the necessity of an accurate interconnect model in the 40 nm technology and beyond is emphasized.      

Materials' impact on interconnect process technology and reliability

We explain how the manufacturing technology and reliability for advanced interconnects is impacted by the choice of metallization and interlayer dielectric (ILD) materials. The replacement of aluminum alloys by copper, as the metal of choice at the 130-nm technology node, mandated notable changes in integration, metallization, and patterning technologies. Those changes directly impacted the reliability performance of the interconnect system. Although further improvement in interconnect performance is being pursued through utilizing progressively lower dielectric constant (low-k) ILD materials from one technology node to another, the inherent weak mechanical strength of low-k ILDs and the potential for degradation in the dielectric constant during processing pose serious challenges to the implementation of such materials in high-volume manufacturing. We consider the cases of two ILD materials, carbon-doped silicon dioxide and low-k spin-on-polymer, to illustrate the impact of the ILD choice on the process technology and reliability of copper interconnects.     

Channel Confinement Enables K Species with Rich Electrons in α-MnO2 for Water Molecules Activation

Water molecules are actively involved in many catalytic oxidation processes, which require the construction of highly active sites for their activation to accelerate the reaction rate, especially over non-noble metal catalysts. Herein, K species is embeded into the natural 2*2 channel of α-MnO₂ by a hydrothermal coupled molten salt method, which would make these K species behave in an electron-rich state and provide more electrons for the activation of water molecules. Compared with surface K modification (namely, the electron-deficient K species), channel K confinement can lower the activation energy barrier of H₂O dissociation on α-MnO₂ to generate hydroxyl species with more nucleophilic oxygen atoms, contributing to the superior HCHO catalytic oxidation activity with a fourfold enhancement. The internal relationship among the confined channel, K species, and catalytic performance is systematically elucidated at the molecular level. This work offers a new ion confinement method and opens up new avenues to construct electron-rich metal sites with channel structures for the activation of water molecules.     

Parameter Modeling for Wafer Probe Test

This paper presents the simulation of parameters for wafer probe test by finite-element modeling with consideration of probe over-travel (OT) distance, scrub, contact friction coefficient, probe tip shapes, and diameter. The goal is to minimize the stresses in the device under the bond pad and eliminate wafer failure in probe test. In the probe test modeling, a nonlinear finite-element contact model is developed for the probe tip and wafer bond pad. Modeling results have shown that the probe test OT, probe tip shape and tip diameters, contact friction between the probe tip and bond pad, as well as the probe scrub of the probe tip on bond pad are important parameters that impact the failure of interlayer dielectric (ILD) layer under bond pad. Comparison between probe test damage and wire bonding failure shows the degree of damage to both probe test and wire bonding on the same bond pad structures. In addition that, a design of experiment (DOE) probe test with different ILD and metal thickness is carried. The correlation between the modeling and the DOE test is studied. The results show that the modeling solution agrees with the DOE probe test data. Modeling results have further revealed that probe test can induce the local tensile (or bending) first principal stress in ILD layer, which may be a root cause of the ILD failure in probe test.     

Robust Low Oxygen Content Cu Alloy for Scaled-Down ULSI Interconnects Based on Metallurgical Thermodynamic Principles

A low oxygen content (LOC) CuAl alloy with no barrier metal (Ta) oxidation was obtained using an oxygen absorption process based on metallurgical thermodynamic principles. LOC CuAl dual damascene interconnects (DDIs) were successfully implemented into 45-nm-node LSIs with 140-nm-pitched lines and 70-nm-diameter $(phi)$ vias. An oxygen absorber of very thin Al film, which was deposited on an electrochemically deposited (ECD) Cu film, captured the oxygen atoms in the ECD Cu due to its larger negative change in the standard Gibbs-free energy of oxidation than in the Cu and the barrier (Ta), preventing the Ta barrier from oxidizing during high-temperature annealing. The high-quality Cu/barrier interface in the LOC CuAl DDIs remarkably improved the via reliability against stress-induced voiding and electromigration. No reliability degradation of the 70-nm-$phi$ vias was observed in the 45-nm-node LOC CuAl DDIs, while keeping the scalability from the 65-nm-node generation.      

Scalability study of laser-induced vertical make-link structure

The scalability of a direct metal-to-metal connection between two different levels of metallizations has been extrapolated to be compatible with modern semiconductor fabrication technology. A simple equation to evaluate the scalability was formulated based on focused ion beam (FIR) cross-sectional images of larger link structures with various sizes. With a 0.6-μm-thick metal 1 line and a 0.5-μm-thick interlevel dielectric (ILD), a width of less than 0.5 μm is evaluated to be possible for the metal 1 line. Two limitations exist in the process of scaled-down link structures, which are the ratio of the thickness of ILD to the thickness of the metal 1 line, t_ILD/t _m, and the quality of laser beam parameters including the spot size and positioning error. However, modern processing technologies and advanced laser processing systems are considered to allow the scalability of a vertical make-link structure. Two layouts of two-level interconnects were designed with increased interconnect densities with a 1-μm pitch of a 0.5-μm-wide metal 1 line. These results demonstrate the application of commercially viable vertical linking technology to very large-scale integration (VLSI) applications     

金刚石膜电极电化清洗中pH值的影响

利用硼掺杂金刚石膜电极在电解液中作阳极,通过控制各种相关条件使电解液中产生大量氢氧自由基和其他强氧化物质,将有机污染物氧化分解成小分子,甚至是CO2和H2O;同时配合专用清洗剂,极好地去除材料表面及狭缝中的固体颗粒和金属杂质,有效实现了被清洗表面的高度洁净化。通过实验分析了pH值的变化对电解液氧化性的影响,确定了最佳pH值为12.5。