Fast thermal analysis for fixed-outline 3D floorplanning

Three dimensional integrated circuits (3D ICs) can alleviate the problem of interconnection, a critical problem in the nanoscale era, and are also promising for heterogeneous integration. However, the thermal challenge in industry is one of key obstacles to adopt the 3D ICs technology. Various thermal analysis models for 3D IC have been proposed in literature. However, the long simulation cycle makes runtime of thermal management inefficient during floorplanning phase. In this paper, we propose a fast thermal analysis method for fixed-outline 3D floorplanning. Before floorplanning, we simulate the thermal distribution of each block placed on different positions. Based on the simulated thermal profiles, bilinear interpolation is adopted to quickly estimate temperature during floorplanning. After the block planning, a heuristic method, which combines the shortest path and min-cost-max-flow, is presented for TSV allocation with minimization of chip temperature and wirelength. Compared with the superposition of thermal profiles method, the proposed thermal analysis method can reduce the peak temperature by 6.7% on average with short runtime for 3D fixed-outline floorplanning, which demonstrates the efficiency and effectiveness of the proposed thermal analysis method.     

满足各种挑战的WCSP封装持续增长

晶圆级芯片尺寸封装（WCSP）消除了类似传统的芯片键合、引线键合和倒装芯片贴装过程的封装工序。这种办法可以为半导体产品用户实现更快的上市时间。WCSP封装应用空间正在扩大到新的领域,并根据管脚数量和器件类型进行细分。WCSP封装正在集成无源、分立元件、射频和存储器器件方面得到应用,并扩展到逻辑集成电路和MEMS器件。但伴随着这种应用的增长出现了很多问题,其中包括随着芯片尺寸和管脚数量的增长对电路板可靠性的影响。概述当今的挑战,以及这些集成和硅通孔技术的未来趋势。     

3D封装及其最新研究进展

介绍了3D封装的主要形式和分类。将实现3D互连的方法分为引线键合、倒装芯片、硅通孔、薄膜导线等,并对它们的优缺点进行了分析。围绕凸点技术、金属化、芯片减薄及清洁、散热及电路性能、嵌入式工艺、低温互连工艺等,重点阐述了3D互连工艺的最新研究成果。结合行业背景和国内外专家学者的研究,指出3D封装主要面临的是散热和工艺兼容性等问题,提出应尽快形成统一的行业标准和系统的评价检测体系,同时指出对穿透硅通孔(TSV)互连工艺的研究是未来研究工作的重点和热点。     

SiGe HBT Microprocessor Core Test Vehicle

A major impediment to the continuation of Moore's Law in the years to come is the performance of interconnections in ICs at high frequencies. Microprocessors are using a greater portion of their clock cycle charging and discharging interconnections. Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) provide a fast track technology for the exploration of the effect of interconnections on high-speed computer design. Industry has pursued low-k dielectrics to decrease wire capacitance. Cu metallization has been used to reduce wire resistance which becomes important as the wire dimensions are scaled down. These are not the only issues for high-frequency interconnections. Some other high-frequency issues include coupling, transmission line propagation, skin effects, and dielectric and substrate loss. These phenomena cause signal attenuation, noise, and dispersion in addition to delay. In the limit of zero device delay, interconnection delay will remain in addition to these problems. Wire shortening has been possible using more layers of interconnections, but this approach may be reaching its limit. An unconventional approach, three-dimensional (3-D) integration, attempts to shorten wiring through increased circuit component placement flexibility. The approach considered here for 3-D integration uses wafer-to-wafer aligning and bonding, wafer thinning and deep, high-aspect-ratio Cu via formation. This provides an intimate interconnection between CPU components and an extremely wide path to memory that would be infeasible in conventional or multichip module packaging. This combination of SiGe HBT BiCMOS and 3-D chip stack technologies enables small computing engines in the 16-32-GHz range.     

Three-step pin assignment algorithm for building block layout

A new pin assignment algorithm is proposed which can be used in floorplanning and building block layout to minimise the total wiring length and channel area while satisfying the minimum distance constraint among pin positions on the block boundary. This algorithm can be used in floorplanning in which block shapes are iteratively modified by the channel density obtained as a result of global routing. The proposed pin assignment algorithm occurs in three steps: approximate pin assignment, global routing and detailed pin assignment. Experimental results were obtained using MCNC placement and floorplanning benchmark examples.<>     

Net-based force-directed macrocell placement for wirelength optimization

We propose a net-based hierarchical macrocell placement such that "net placement" dictates the cell placement. The proposed approach has four phases. 1) Net clustering and net-level floorplanning phase: a weighted net dependency graph is built from the input register-transfer-level netlist. Clusters of nets are then formed by clique partitioning and a net-cluster level floorplan is obtained by simulated annealing. The floorplan defines the regions where the nets in each cluster must be routed. 2) Force-directed net placement phase: a force-directed net placement is performed which yields a coarse net-level placement without consideration for the cell placement. 3) Iterative net terminal and cell placement phase: a force-directed net and cell placement is performed iteratively. The terminals of a net are free to move under the influence of forces in the quest for optimal wire length. The cells with high net length cost may "jump" out of local minima by ignoring the rejection forces. The overlaps are reduced by employing electrostatic rejection forces. 4) Overlap removal and input/output (I/O) pin assignment phase: Overlap removal is performed by a grid-based heuristic. I/O pin assignment is performed by minimum-weight bipartite matching. Placements generated by the proposed approach are compared with those generated by Cadence Silicon Ensemble and the O-tree floorplanning algorithm. On average, the proposed approach improves both the total wire length and longest wire length by 18.9% and 28.3%, respectively, with an average penalty of 5.6% area overhead.     

蝶形激光器管脚振动疲劳寿命分析

;针对用引线连接的蝶形激光器管脚在扫频振动测试中发生齐根断裂的问题,文章建立了有限元分析模型,模型中用不同管脚长度反映引线的影响,采用模态叠加法分析了管脚在20 g、20～2000 Hz正弦扫频振动下的应力.基于Miner准则,计算了管脚在振动条件下的寿命.分析结果表明:(1)原激光器管脚的固有频率高于2000 Hz,...     

Driver IC and COG Package Design

This paper investigates the interconnection between the driver integrated circuit (IC) and glass substrate via anisotropic conductive adhesive (ACF) of chip on glass package. The conductive particle deformation is evaluated using a novel method, optical microscope (OM) inspection. The proposed method is more convenient than the traditional approach using scanning electron microscopy applied in the manufacturing process. Interconnection performance is easily judged using OM, allowing poor interconnection between the driver IC and glass substrate to be screened out. Several types of driver ICs with different bump area ratios (total input bump area/total output bump area, input/output ratio) and length/width (L/W) ratios are designed in this experiment. The conductive particle deformations are investigated in this study. Driver ICs with L/W ratios larger than 15 have better conductive particle deformation uniformity at each position. The average deformation degree at the driver IC center position is larger than that at the side and edge positions. The deformation degree at the input position with a smaller bump area is better than that at the output position. The conductive resistance increases with the reliability testing time because of the thermal stress effect and softening of the ACF polymer material. The deformation degree is related to the conductive resistance of the interconnection. The conductive resistance is lower at the center and input positions with larger deformation degree.     

Highly uniform InAlAs-InGaAs HEMT technology for high-speed optical communication system ICs

The authors have developed a highly uniform, InP-based high-electron-mobility transistor (HEMT) technology for high-speed optical communication system integrated circuits (ICs). Special attention was paid to obtaining a high yield and uniformity without degrading the high-frequency characteristics of these HEMTs. An InP etch-stopper layer was employed to control the gate recess etching. The authors successfully fabricated InAlAs-InGaAs HEMTs with a cutoff frequency of 175 GHz after interconnection, which is sufficiently high for application in 40-Gb/s optical communication ICs. The standard deviation of the threshold voltage was only 13 mV across a 3-in wafer. They also developed a fabrication process for a Y-shaped gate to maintain high uniformity, enabling us to integrate more than a thousand transistors with a 0.1-/spl mu/m-class gate length. With this technology, ICs with over 1000 transistors were successfully fabricated and operated at over 40 Gb/s. Furthermore, the authors fabricated a 2:1 multiplexer that had more than 200 transistors and reached an operating speed of 90 Gb/s. They have thus concluded that their InAlAs-InGaAs HEMT technology can be applied to fabricate high-speed ICs for optical communication systems.     

绝缘引线在陶瓷封装中的应用

随着半导体封装持续朝着多引脚、小节距及多列多层叠的方向发展,引线键合技术正面临越来越大的挑战。当陶瓷空封器件中的键合引线长度大于3.0 mm时,在加电冲击试验过程中键合引线容易出现瞬间的短路而导致器件失效。文章主要阐述了产生该问题的基本原因,提出了采用绝缘引线键合解决该问题的可行性,介绍了绝缘引线的基本特性,并用实际封装的电路进行了绝缘引线键合的可靠性研究,根据研究结果,提出了绝缘引线可有限应用于陶瓷封装的结论。     

2TF:一种协同考虑过硅通孔和热量的三维芯片布图规划算法

 三维芯片由多个平面器件层垂直堆叠而成,并通过过硅通孔(TSV,Through Silicon Via)进行层间互连,显著缩短了互连线长度、提高了芯片集成度.但三维芯片也带来了一系列问题,其中单个过硅通孔在目前的工艺尺寸下占据相对较大的芯片面积,且其相对滞后的对准技术亦降低了芯片良率,因此在三维芯片中引入过多的过硅通孔将增加芯片的制造和测试成本.垂直堆叠在使得芯片集成度急剧提高的同时也使得芯片的功耗密度在相同的面积上成倍增长,由此导致芯片发热量成倍增长.针对上述问题,本文提出了一种协同考虑过硅通孔和热量的三维芯片布图规划算法2TF,协同考虑了器件功耗、互连线功耗和过硅通孔数目.在MCNC标准电路上的实验结果表明,本文算法过硅通孔数目和芯片的峰值温度都有较大的降低.     

Si-SiGe材料三维CMOS集成电路技术研究

根据SiGe材料的物理特性,提出了一种新有源层材料的三维CMOS集成电路.该三维CMOS集成电路前序有源层仍采用Si材料,制作nMOS器件;后序有源层则采用SiGe材料,以制作pMOS器件.这样,电路的本征性能将由Si nMOS决定.使用MEDICI软件对Si-SiGe材料三维CMOS器件及Si-SiGe三维CMOS反相器的电学特性分别进行了模拟分析.模拟结果表明,与Si-Si三维CMOS结构相比,文中提出的Si-SiGe材料三维CMOS集成电路结构具有明显的速度优势.     

Si-SiGe材料三维CMOS集成电路技术研究

根据SiGe材料的物理特性,提出了一种新有源层材料的三维CMOS集成电路.该三维CMOS集成电路前序有源层仍采用Si材料,制作nMOS器件;后序有源层则采用SiGe材料,以制作pMOS器件.这样,电路的本征性能将由Si nMOS决定.使用MEDICI软件对Si-SiGe材料三维CMOS器件及Si-SiGe三维CMOS反相器的电学特性分别进行了模拟分析.模拟结果表明,与Si-Si三维CMOS结构相比,文中提出的Si-SiGe材料三维CMOS集成电路结构具有明显的速度优势.     

Planar multilevel interconnection technology employing a polyimide

A planar multilevel interconnection technology, called planar metallization with polymer (PMP), has been developed, which utilizes a polyimide known as PIQ (polyimide isoindroquinazoline-dione) as an interlevel dielectric. The PIQ is highly resistant to heat and is mechanically flexible. Its low impurity concentrations also make it very stable in semiconductors. The PMP processing techniques have been refined to the stage where ICs can be fabricated commercially. A PIQ film etchant forms fine via-holes up to 3/spl times/3 /spl mu/m/SUP 2/, and chip size can be reduced by placing bonding pads on the active region of the device. Highly reliable linear and 256-bit bipolar memory ICs have been realized through this technology.     

高性能可编程互连资源设计研究

传统的可编程互联结构在短距离互连上往往采用单管、中距离上有双向线,这使得在CLB中查找表(LUT)数目变大后,互连上的延迟会随线长增加而呈指数增长.本文提出了一种改进的高性能互连结构,改进了短、中和长距离互连,使得其在CLB中LUT数目增加的情况下让芯片拥有更好的互连延迟特性,通过对这种互连结构和传统的互连结构进行建模...     

Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications

Future inter- and intra-ULSI interconnect systems demand extremely high data rates (up to 100 Gbps/pin or 20-Tbps aggregate) as well as bidirectional multiI/O concurrent service, re-configurable computing/processing architecture, and total compatibility with mainstream silicon system-on-chip and system-in-package technologies. In this paper, we review recent advances in interconnect schemes that promise to meet all of the above system requirements. Unlike traditional wired interconnects based solely on time-division multiple access for data transmission, these new interconnect schemes facilitate the use of additional multiple access techniques including code-division multiple access and frequency-division multiple access to greatly increase bandwidth and channel concurrency as well as to reduce channel latency. The physical transmission line is no longer limited to a direct-coupled metal wire. Rather, it can be accomplished via either wired or wireless mediums through capacitor couplers that reduce the baseband noise and dc power consumption while simplifying the fabrication process by eliminating vertical metal studs needed in three-dimensional ICs. These new advances in interconnect schemes would fundamentally alter the paradigm of ULSI data communications and enable the design of next-generation computing/processing systems.     

基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

一种考虑自热效应的互连线缓冲器插入优化模型

Considering the self-heating effect,an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented.Based on the proposed resistance model and according to the trade-off theory,a novel optimization analytical model of delay,power dissipation and bandwidth is derived.The proposed optimal model is verified and compared based on 90 nm,65 nm and 40 nm CMOS technologies.It can be found that more optimum results can be easily obtained by the proposed model.This optimization model is more accurate and realistic than the conventional optimization models,and can be integrated into the global interconnection design of nano-scale integrated circuits.     

Edge effect aware low-power crosstalk avoidance technique for 3D integration

Metal wires and through silicon vias (TSVs) are frequently performance bottlenecks of 3D ICs due to their high capacitive crosstalk which can be reduced using coding techniques. In this work we show that existing TSV crosstalk avoidance codes (CACs) are impractical for real applications due to the edge effects in TSV bundles. Additionally, these 3D CACs do not reduce the metal wire crosstalk and dramatically increase the power consumption of 2D and 3D interconnects. This work presents a 3D CAC which overcomes previous limitations. The method is based on an intelligent fixed mapping of the bits of existing 2D CACs onto rectangular or hexagonal TSV arrangements. Simulation results, obtained by circuit simulations in combination with an electromagnetic field solver, show that existing 3D CACs only reduce the TSV crosstalk by a maximum of 9.4%, provide no optimization of the metal wire crosstalk and induce an increase in the interconnect power consumption by about 50%. In contrast, the presented technique requires less hardware and reduces the maximum crosstalk of modern TSV and metal wire buses by 37.8% and 47.6%, respectively, while leaving their power consumption almost unaffected. Alternatively, our technique can reduce the TSV and metal wire crosstalk peaks by 20.3% and 47.7%, respectively, while additionally providing a reduction in the TSV and metal wire power consumption by 5.3% and 21.9%, respectively.     

塑料封装铜丝内连电子元器件开封新工艺研究

采用两种开封工艺对塑料封装、铜丝内连的电子元器件进行了开封实验.通过自动开封机对开封工艺参数的精确控制,使用浓硝酸与浓硫酸的混合液对样件进行开封,比较完整的保留了铜丝内连结构,达到了开封测试的基本要求.另外通过在混合腐蚀液中添加过量CuSO4·5H2O晶体使腐蚀液中的Cu2 在开封过程中始终保持饱和溶解状态下进行手工开封,结果表明改进后的腐蚀液对铜丝及铜球焊点的腐蚀破坏得到有效抑制.研究结果对于解决塑料封装、铜丝内连电子器件开封测试的难题具有指导意义.