Design and fabrication of 94 GHz MMIC single balanced resistive mixer without IF balun

In this paper, a 94 GHz microwave monolithic integrated circuit (MMIC) single balanced resistive mixer affording high LO-to-RF isolation was designed without an IF balun. The single balanced resistive mixer, which does not require an external IF balun, was designed using a 0.1 μm InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (HEMT). The designed MMIC single balanced resistive mixer was fabricated using the 0.1 μm MHEMT MMIC process. From the measurement, conversion loss of the single balanced resistive mixer was 14.7 dB at an LO power of 10 dBm. The P_1 dB (1 dB compression point) values of the input and output were 10 dBm and −5.3 dBm, respectively. The LO-to-RF isolation of the single balanced resistive mixer was −35.2 dB at 94.03 GHz. The single balanced resistive mixer in this work provided high LO-to-RF isolation without an IF balun.     

High performance quadruple sub-harmonic mixer for millimeter-wave applications

In this paper, we present high performance quadruple sub-harmonic mixers for millimeter-wave applications. The sub-harmonic mixer was designed by using 0.1 μm GaAs PHEMT's and the coplanar wave-guide library. We show the low conversion loss of 5.8 dB at a local oscillator (LO) power of 13 dBm from the fabricated sub-harmonic mixers. The V-band sub-harmonic mixer also ensure a high degree of isolation showing −75.0 dB in the LO-to-IF and −48.1 dB in the LO-to-RF at a frequency of 14.5 GHz, respectively. The fabricated V-band sub-harmonic mixer has a lower conversion loss characteristics compared with ever reported mixers for millimeter frequencies.     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

An 863-870 MHz spread-spectrum FSK transceiver design for wireless sensor

Simulation results of a 863-870 MHz frequency-hopped spread-spectrum (FHSS) transceiver with binary frequency shift keying (BFSK) modulation at 20 kb/s for wireless sensor applications is presented.The transmit/receive RF front end contains a BFSK modulator, an upconversion mixer, a power amplifier (PA), and an 863-870 MHz band pass filter (BPF) at the transmitter side and a low-noise amplifier with down conversion mixer to zero-IF, a low-pass channel-select filter, a limiter and a BFSK demodulator at the receiver side. The various block parameters of the transmit/receive RF front end like noise figure (NF), gain, 1 dB compression point (P-1 dB), and IIP3 are simulated and optimized to meet low power and low cost transceiver specifications.The transmitter simulations show an output ACPR (adjacent channel power ratio) of −22 dBc, 3.3 dBm P-1 dB of PA, and transmitted power of 0 dBm. The receiver simulations show 51.1 dB conversion gain, −7 dBm IIP3, −15 dB return loss (S11), and 10 dB NF. Low power arctangent-differentiated BFSK demodulator has been chosen and the BER performance has been co simulated with the analog receiver. The complete receiver achieves a BER of 10⁻³ at 10.5 dB of EbtoNo. The transceiver simulations show an RMS frequency error of 1.45 kHz.     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology

This paper describes the design of a 1.9-GHz front-end receiver. The target application of the receiver is the personal communications standard PCS1900. Powered by a 1-V supply, the receiver consists of a low noise amplifier (LNA) and a downconversion mixer. The receiver was fabricated within a 0.5-μm CMOS technology. The LNA features 15 dB of gain and a 1.8-dB noise figure. The mixer exhibits 1.5-dB conversion loss, 12-dB noise figure, and 0 dBm 1 dB-compression point     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A 0.18μm CMOS gain-switched LNA and mixer with large dynamic range

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier （LNA） and a passive mixer with no external balun for near-zero-IF （Intermediate Frequency）/RF （Radio Frequency） applications are described. The LNA, fabricated in the 0.18μm 1P6M CMOS technology, adopts a gain-switched technique to increase the linearity and enlarge the dynamic range. The mixer is an IQ-based passive topology. Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω. Combining LNA and mixer, the front-end measured performances in high gain state are： -15dB of Sll, 18.5dB of voltage gain, 4.6dB of noise figure, 15dBm of IIP3, 85dBm to -10dBm dynamic range. The full circuit drains 6mA from a 1.8V supply.     

A 0.18μm CMOS GAIN-SWITCHED LNA AND MIXER WITH LARGE DYNAMIC RANGE

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier(LNA) and a passive mixer with no external balun for near-zero-IF(Intermediate Frequency)/RF(Radio Frequency) applications are described.The LNA,fabricated in the 0.18μm 1P6M CMOS technology,adopts a gain-switched technique to increase the linearity and enlarge the dynamic range.The mixer is an IQ-based passive topology.Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω.Combining LNA and mixer,the front...     

Tunable wideband SAW-less receiver front-end in 65 nm CMOS

A surface acoustic wave-less receiver front-end for GSM, TD-LTE and TD-SCDMA standards featuring a novel low noise amplifier (LNA) architecture and harmonic rejection technique is presented. The two-stage LNA uses capacitive feedback in the first stage for wideband input matching. It can operate from 500 MHz up to 2.5 GHz with an S₁₁ below ?15 dB. The harmonic rejection mixer structure operates using two- and four-phase local oscillator signals and is capable of achieving a high harmonic rejection over a wide channel bandwidth. The average harmonic rejection is above 60 dB measured over a 20 MHz LTE channel and above 70 dB over a GSM channel. The mixer structure contains digitally tunable resistor and capacitor banks for precise tuning, causing the peak harmonic rejection in the channel to exceed 80 dB. The precise tuning capability ensures good harmonic rejection in the presence of process mismatch and duty cycle mismatch. The 1-dB received signal compression point with a blocker present at 20/80 MHz offset for low-/high-band is 0 and +2 dBm, respectively. In-band IIP3, and IIP2 are ?14.8 and >49 dBm, respectively, for low-band. For high-band they are ?18.2 and >44 dBm. Implemented in 65 nm CMOS, the complete front-end consumes 80 mW of power.     

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier(LNA) and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm~2 die size.     

Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13 $mu$m CMOS

A 2.1 GHz CMOS front-end with a single-ended low-noise amplifier (LNA) and a double balanced, current-driven passive mixer is presented. The LNA drives an on-chip transformer load that performs single-ended to differential conversion. A detailed comparison in gain, noise, and second and third order linearity performance is presented to motivate the choice of a current-driven passive mixer over an active mixer. The front-end prototype was implemented on a 0.13 $mu$m CMOS process and occupies an active chip area of 1.1 mm $^{2}$. It achieves 30 dB conversion gain, a low noise figure of 3.1 dB (integrated from 40 KHz to 1.92 MHz), an in-band IIP3 of ${-}$12 dBm, and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5 V power supply.      

一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

A new CMOS wideband low noise amplifier with gain control

In this paper, a new CMOS wideband low noise amplifier (LNA) is proposed that is operated within a range of 470 MHz-3 GHz with current reuse, mirror bias and a source inductive degeneration technique. A two-stage topology is adopted to implement the LNA based on the TSMC 0.18-μm RF CMOS process. Traditional wideband LNAs suffer from a fundamental trade-off in noise figure (NF), gain and source impedance matching. Therefore, we propose a new LNA which obtains good NF and gain flatness performance by integrating two kinds of wideband matching techniques and a two-stage topology. The new LNA can also achieve a tunable gain at different power consumption conditions. The measurement results at the maximum power consumption mode show that the gain is between 11.3 and 13.6 dB, the NF is less than 2.5 dB, and the third-order intercept point (IIP3) is about −3.5 dBm. The LNA consumes maximum power at about 27 mW with a 1.8 V power supply. The core area is 0.55×0.95 mm².     

Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end

A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-μm 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point (P_-1 dB)(P_{{-1}\,{\rm dB}}) of −13.5 dBm and the input-referred third-order intercept point (P _IIP3) of −1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of 1.45 ×0.721.45 \times 0.72 mm² including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies.     

2.4GHz带片上非平衡变压器射频前端的设计与优化

本文介绍了一种工作在2.4GHz频段的低功耗、低噪声、高线性射频接收机前端电路,该接收前端电路使用新型的带三种增益模式的LNA,并提出一种新的片上非平衡变压器优化技术。前端电路采用了直接变频结构,使用片上非平衡变压器实现低噪声放大器与下变频混频器之间的单端-差分转换,优化设计以提高前端电路的噪声性能。本文使用锗硅0.35um BiCMOS工艺,所采用的技术同样适用于CMOS工艺。前端电路总的最大转换增益为36dB;在高增益模式下的双边带噪声系数为3.8dB;低增益模式下,输入三阶交调点位12.5dBm。为了获得最大的输入动态范围,低噪声放大器采用三种可调增益模式,低增益模式使用by-pass结构,大大提高了大信号输入下接收前端的线性度。下变频混频器在输出端使用可调R-C tank,滤除带外高频杂波。混频器输出使用射极跟随器作为输出极驱动片外50ohm负载。该接收前端在2.85-V电源供电下,功耗为33mW,芯片面积为0.66mm2。     

A dual-band reconfigurable direct-conversion receiver RF front-end

6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm2.     

A 12-mW wide dynamic range CMOS front-end for a portable GPSreceiver

This paper describes a CMOS low-noise amplifier (LNA) and mixer intended for use in the front-end of a global positioning system (GPS) receiver. The circuits were implemented in a standard 0.35-μm (drawn) CMOS process, with one poly and two metal layers. The LNA has a forward gain (S21) of 17 dB and a noise figure of 3.8 dB. The mixer has a voltage conversion gain of -3.6 dB and a third-order intermodulation intercept point (IP3) of 10 dBm, input referred. The combination draws 12 mW from a 1.5-V supply     

Design techniques for mitigation of intermodulation distortion components in CMOS RF receiver front-end circuits with subthreshold operation

This paper provides an overview of target applications and design aspects for emerging radio frequency front-end circuits with subthreshold biasing to reduce power consumption. Design methods are described to linearize a subthreshold pseudo-differential common-source cascode low-noise amplifier (LNA) and a subthreshold active mixer. The linearization techniques can improve the third-order intermodulation intercept point (IIP3) through the use of passive components, which implies that they do not require auxiliary amplifiers to suppress third-order distortion components, and therefore do not incur any extra power consumption. A 1.95 GHz receiver front-end chip with a narrowband LNA and down-conversion mixer was designed and fabricated in 110 nm CMOS technology. Measurement results show that the linearized low-power front-end has a 20.6 dB voltage gain, a 9.5 dB double sideband noise figure, and a ? 10.8 dBm IIP3 with a power consumption of 0.9 mW.