An investigation of ultra low-k dielectrics with high thermal stability for integration in memory devices

For the PMD in a next generation memory device, two kinds of newly developed ultra low-k MSQ materials (k < 2.0) are shown to have good thermal stability, up to 600 °C, while the investigated HSQ (k = 2.9) material degraded at temperatures >500 °C. The thermal stability of the low-k MSQ is correlated with the amount of Si-X (X = H or CH₃), the ratio of Si-X to Si-O, and the structure of the Si-O bonds. With PE-SiO₂ and PE-SiN capping on HSQ, the k-value of  < 3.0 can be maintained up to 800 °C due to Si-H remaining in the film. Similarly, PE-SiC and PE-SiO₂ capping increases the k-value degradation onset temperature of the MSQ materials by 50 °C.     

Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

This paper reports the design, assembly and reliability assessment of 21 × 21 mm² Cu/low-k flip chip (65 nm node) with 150 μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low-k layers, Metal Redistribution Layer (RDL) and Polymer Encapsulated Dicing Lane (PEDL) are applied to the Cu/low-k wafer. Lead-free Sn2.5Ag, high-lead Pb5Sn and Cu-post/Sn37Pb bumps are evaluated as the first-level interconnects. It is found that the flip chip assembly of high-lead bumped test vehicle requires the right choice of flux and good alignment between the high-lead solder bumps and substrate pre-solder alloy to ensure proper solder bump and substrate pre-solder alloy wetting. Joint Electron Device Engineering Council (JEDEC) standard reliability is performed on the test vehicle with different first-level interconnects, underfill materials and PEDL.By integrating PEDL to the Cu/low-k chip, the reliability performance of the flip chip package has been improved by almost two times. This paper has demonstrated Moisture Sensitivity Test-Level 2 (MST-L2) qualified large die and fine-pitch Cu/low-k flip chip package. The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/low-k generations.     

Gentle FUSI NiSi metal gate process for high-k dielectric screening

In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).     

Repair of plasma-damaged p-SiOCH dielectric films in supercritical CO2

The silylation of plasma-damaged p-SiOCH low-k dielectric films was investigated with trimethychlorosilane (TMCS), hexamethyldisilazane (HMDS) and dimethyldichlorosilane (DMDCS) dissolved in supercritical CO₂ (scCO₂) and the effect of thermal pre-treatment on the repair performance was also studied. The surface hydrophobicity was rapidly recovered by silylation and the order of recovery efficiency was HMDS (85.4°) > DMDCS (83.4°) > TMCS (75.0°). The FTIR analyses revealed that the restoration to the original state was not achieved over various reaction conditions (up to 31 MPa, 85 °C, and 3 h reaction time). After pre-treatment in a vacuum cell at 250 °C, the Si-O-Si peak intensity increased slightly, and the surface hydrophobicity was partially recovered to 54.4° due to the removal of physically adsorbed H₂O molecules as well as some extent of dehydration of neighboring surface silanol groups. The hydrophobicity increased to 84.4° after subsequent treatment with HMDS in scCO₂. From DSIMS, the carbon concentration did not increase in bulk region after silylation of thermally pre-treated low-k films.     

Impact of barrier deposition process on electrical and reliability performance of Cu/CVD low k SiOCH metallization

Integration of Cu with low k dielectrics provided solution to reduce both resistance-capacitance time delay and parasitic capacitance of BEOL interconnections for 130 nm and beyond technology node. The motivation of this work is to study and improve electrical and reliability performance of two-level Cu/CVD low k SiOCH metallization from the results of diffusion barrier deposition schemes. Barrier deposition schemes are (a) high-density-plasma 250 Å Ta; (b) surface treatment of forming gas followed by high-density-plasma 250 Å Ta and (c) bi-layer of 100 Å Ta(N)/150 Å Ta. In this work, we demonstrated the superior and competency of high-density-plasma Ta deposition for Cu/CVD low k metallization and achieved excellent electrical and reliability results. Wafers fabricated with high-density-plasma Ta barrier scheme resulted in the best electrical yields, >90% for testing vehicles of dense via chains (via size=200 nm) and interspersed comb structures (width/space=200 nm/200 nm). Dielectric breakdown strength of the interspersed comb structures obtained at electric field of 0.3 MV/cm was ∼4 MV/cm.     

Microstructure and stress in high-k Hf-Y-O thin films

We investigated the microstructure and the stress of high-k Hf-Y-O thin films deposited by atomic layer deposition (ALD). These hafnium oxide based films with a thickness of 5-60 nm stabilized in crystal structure with yttrium oxide by alternating the Hf- or Y-containing metal precursor during deposition. The microstructure was investigated by XRD and TEM in dependence of substrate and deposition temperature. The film stress was monitored during thermal cycles up to 500 °C using the substrate curvature method on (1 0 0)-Si wafer material with or without 10 nm TiN bottom electrode as well as on fused silica. It was observed that crystallinity and phases are depending on deposition temperature and film thickness. During thermal treatment the films crystallize depending on deposition temperature, yttrium content and substrate material at different temperatures. Crystallization of the films depends strongly on yttrium content. The highest reduction of 720 MPa was observed for films deposited with a Hf:Y cycle ratio of 10:1 where 6.2% of all metal atoms are replaced by yttrium. These Hf-Y-O films also show the highest k-value of 29 and have the smallest thermal expansion coefficient mismatch to TiN electrodes. Therefore we conclude that Hf-Y-O films are candidates for application in next generations of microelectronic MIM-capacitor devices or metal gate transistor technology.     

32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k = 2.3

A 32 nm node BEOL integration scheme is presented with 100 nm metal pitch at local and intermediate levels and 50 nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32 nm RC performance specifications, extreme low-k (ELK) porous SiOCH k = 2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k = 2.3 is investigated using a multi-level metallization test vehicle in a 45 nm mature generation.     

Studies on dielectric relaxation and defect generation for reliability assessments in ultrathin high-k gate dielectrics on Ge

In this work, we present the results of dielectric relaxation and defect generation kinetics towards reliability assessments for Zr-based high-k gate dielectrics on p-Ge (1 0 0). Zirconium tetratert butoxide (ZTB) was used as an organometallic source for the deposition of ultra thin (∼14 nm) ZrO₂ films on p-Ge (1 0 0) substrates. It is observed that the presence of an ultra thin lossy GeO_x interfacial layer between the deposited high-k film and the substrate, results in frequency dependent capacitance-voltage (C-V) characteristics and a high interface state density (∼10¹² cm⁻² eV⁻¹). Use of nitrogen engineering to convert the lossy GeO_x interfacial layer to its oxynitride is found to improve the electrical properties. Magnetic resonance studies have been performed to study the chemical nature of electrically active defects responsible for trapping and reliability concerns in high-k/Ge systems. The effect of transient response and dielectric relaxation in nitridation processes has been investigated under high voltage pulse stressing. The stress-induced trap charge density and its spatial distribution are reported. Charge trapping/detrapping of stacked layers under dynamic current stresses was studied under different fluences (−10 mA cm⁻² to −50 mA cm⁻²). Charge trapping characteristics of MIS structures (Al/ZrO₂/GeO_x/Ge and Al/ZrO₂/GeO_xN_y/Ge) have been investigated by applying pulsed unipolar (peak value - 10 V) stress having 50% duty-cycle square voltage wave (1 Hz-10 kHz) to the gate electrode.     

Variation in process conditions of porogen-based low-k films: A method to improve performance without changing existing process steps in a sub-100 nm Cu damascene integration route

This article describes less explored solutions to improve interconnect performance without changing established steps (etch, strip, clean, CMP) in a sub-100 nm integration route. Process conditions of the porogen-based low-k are adjusted by (1) varying the curing time (2) adding a thermal anneal step prior to CuO reduction or (3) depositing a capping layer on top of the low-k after curing. The low-k material examined in this study is Aurora^® ELK HM (k ∼ 2.5).The integration process was robust against these variations, showing good electrical yield for all process splits. RC-product was improved when using a shorter curing time and when an anneal step prior to CuO reduction was performed. The use of a thicker capping layer decreased capacitance, showing an improved protection against damage.     

Trap parameters and conduction mechanism in HfO2-Ta2O5 mixed stacks in response to microwave irradiation

The effect of microwave treatment at room temperature on the leakage current and mechanisms of conductivity in mixed HfO₂-Ta₂O₅ (10 nm) stacks has been studied by temperature dependent (20-100 °C) current-voltage characteristics. It was established that the short term irradiation (∼6 s) affects the electrically active centers in the mixed oxide, provokes modification of the dominant conduction mechanism at about and above 1 MV/cm and improves the temperature stability of capacitors manifesting as low level of current at high temperatures (current decrease up to two orders of magnitude at 100 °C after the treatment is detected). The traps involved in the conduction processes in pre- and post-irradiation capacitors are identified. The longer exposure (10-15 s) is effective in a significant reduction of leakage current (up to 3-4 orders of magnitude in wide range of applied voltages). The potential of microwave treatment at room temperature as technological step for improving the temperature stability of leakage current in high-k stacked capacitors is discussed.     

Theoretical study of mechanical properties of multi-layer ULSI interconnect dielectrics by surface acoustic wave method

The surface acoustic waves (SAWs) technique is becoming an attractive tool for accurately and nondestructively characterizing the mechanical property of the fragile low dielectric constant (low-k) thin film used in the advanced ULSI multi-layer interconnects. The dispersion features of SAWs propagating on the layered structure of low-k/SiO₂/Si substrate and low-k/Cu/Si substrate are investigated in detail. The influence of the film thickness on the dispersion curvature is provided as an instruction for an accurate and facile fitting process. Numerical results indicate that the mechanical property of low-k films is expected to determine effectively when the broadband frequency is up to 300 MHz.     

Adhesion study of tetra methyl cyclo tetra siloxanes (TMCTS) and tri methyl silane (3MS)-based low-k films

Chemical vapor deposited (CVD) low-k films using tri methyl silane (3MS) precursors and tetra methyl cyclo tetra siloxanes (TMCTS) precursors were studied. Films were deposited by means of four processes, namely, O₂, O₂ + He process and CO₂, CO₂ + O₂ process for 3MS and TMCTS precursors, respectively. Interfacial adhesion energy (G_c), of low-k/Si samples, as measured by a 4-point bending test displayed a linear relationship with film hardness and modulus. Fractography studies indicated two possible failure modes with the primary interface of delamination being either at low-k/Si or Si/epoxy interface. In the former, once delamination initiated at the low-k/Si interface, secondary delamination at the Si/epoxy and epoxy/low-k interfaces was also observed. Films with low hardness (<5 GPa) displayed a low G_c (<10 J/m²) with an adhesive separation of Si/epoxy, epoxy/low-k, and low-k/Si interfaces. Whereas, films of high hardness (>5 GPa) displayed interfacial energies in excess of 10 J/m² with separation of Si/epoxy and epoxy/low-k interfaces, thus indicating excellent adhesion between the Si and low-k films. Films with high hardness have less carbon in the system causing it to be more “silicon dioxide” like and exhibiting better adhesion with the Si substrate.     

The structural and electrical properties of the SrTa2O6/In0.53Ga0.47As/InP system

The structural and electrical properties of SrTa₂O₆(SrTaO)/n-In_0.53GaAs_0.47(InGaAs)/InP structures where the SrTaO was grown by atomic vapor deposition, were investigated. Transmission electron microscopy revealed a uniform, amorphous SrTaO film having an atomically flat interface with the InGaAs substrate with a SrTaO film thickness of 11.2 nm. The amorphous SrTaO films (11.2 nm) exhibit a dielectric constant of ∼20, and a breakdown field of >8 MV/cm. A capacitance equivalent thickness of ∼1 nm is obtained for a SrTaO thickness of 3.4 nm, demonstrating the scaling potential of the SrTaO/InGaAs MOS system. Thinner SrTaO films (3.4 nm) exhibited increased non-uniformity in thickness. From the capacitance-voltage response of the SrTaO (3.4 nm)/n-InGaAs/InP structure, prior to any post deposition annealing, a peak interface state density of ∼2.3 × 10¹³ cm⁻² eV⁻¹ is obtained located at ∼0.28 eV (±0.05 eV) above the valence band energy (E_v) and the integrated interface state density in range E_v + 0.2 to E_v + 0.7 eV is 6.8 × 10¹² cm⁻². The peak energy position (0.28 ± 0.05 eV) and the energy distribution of the interface states are similar to other high-k layers on InGaAs, such as Al₂O₃ and LaAlO₃, providing further evidence that the interface defects in the high-k/InGaAs system are intrinsic defects related to the InGaAs surface.     

Etching characteristics of photoresist and low-k dielectrics by Ar/O2 ferrite-core inductively coupled plasmas

We have investigated the characteristics of Ar/O₂ plasmas in terms of the photoresist (PR) and low-k material etching using a ferrite-core inductively coupled plasma (ICP) etcher. We found that the O₂/(O₂+ Ar) gas flow ratio significantly affected the PR etching rate and the PR to low-k material etch selectivity. Fourier transform infrared spectroscopy (FTIR) and HF dipping test indicated that the etching damage to the low-k material decreased with decreasing O₂/(O₂ + Ar) gas flow ratio.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

Electromigration resistance and long term stability of textured silver thin films on LTCC

Silver (Ag) is regarded as advanced material for metallization purposes in microelectronic devices because of its high conductivity and its enhanced electromigration resistance. Besides the typical use of silicon based substrate materials for device fabrication, thin film metallization on ceramic and glass-ceramic LTCC (low temperature co-fired ceramics) substrates gets more and more into focus as only thin film technology can provide the required lateral resolutions of structures in the μm-range needed for e.g. high frequency applications. Therefore, the reliability of Ag thin films is investigated under accelerated aging conditions, utilizing test structure which consists of 5 parallel lines stressed with current densities up to 1.5 × 10⁷ A cm⁻² at temperatures ranging from room-temperature up to 300 °C. To detect the degradation via the temporal characteristics of the current signal a constant voltage is applied taking the overall resistance of the test structure into account. The mean time to failure of the Ag metallization substantially depends on the degree of (1 1 1)-orientation which, in turn, is strongly affected by the plasma power P_P during deposition. Therefore, Ag thin films deposited at P_P = 1000 W feature a 7 times higher reliability than those deposited at P_P = 100 W. Due to the enhanced stability of grains being (1 1 1)-oriented in textured thin films the material transport predominantly occurs along grain boundaries, whereas in Ag films without a (1 1 1)-orientation volume-related diffusion effects dominate due to the lower stability of these grains.     

A robust k ∼ 2.3 SiCOH low-k film formed by porogen removal with UV-cure

Aurora^®ELK films were fabricated by PE-CVD of a SiCOH matrix precursor and an organic porogen material. The porogen material is removed during a subsequent thermally assisted UV-cure step with a short wavelength UV-lamp (λ < 200 nm). This results in film thickness shrinkage of 13.2% and a robust low-k film with k-value ∼ 2.3, elastic modulus ∼5.0 GPa and intrinsic film stress ∼59 MPa. The microscopic film properties during UV-cure were evaluated by FT-IR. A decrease in the CH_x peak area is related to the porogen removal from the film resulting in a reduced dielectric constant. The decrease of the Si-CH₃ peak and increase in the SiO network area are associated to the network restructuring and increase in elastic modulus. The nature of the Si-H peaks which appear during UV-cure has to be investigated carefully to determine their impact on film reliability. The dielectric diffusion barrier can work as an UV absorption layer which reduces UV-curing of underlying layers and possible UV reflections on interfaces. The SiCN/A-SiCO diffusion barrier film properties during UV-cure show a decrease in k-value, increase in intrinsic film stress and a slight increase in leakage. More research is needed to evaluate the impact of porogen removal by UV-cure on BEOL integration.     

Thermal stability and gap-fill properties of spin-on MSQ low-k dielectrics

Looking onto integration of low-k materials within FEOL used processing temperatures in this field are much higher than within BEOL. In addition partly high aspect ratio features have to be filled without defects, e.g. within usage of spin-on low-k materials for shallow trench isolation. We evaluated two MSQ-based spin-on dielectrics, a porous ultralow-k material and a dense spin-on glass regarding their thermal stability and gap-fill behaviour. The films were annealed from standard curing temperatures up to temperatures of 850 °C and 900 °C, film thickness and refractive index were measured by spectral ellipsometry, electrical film properties were evaluated by a mercury probe measurement and changes within chemistry are studied by FTIR. Both low-k materials are thermally stable up to temperatures of 650-700 °C. Above this range the film thickness is rapidly decreasing, refractive index and corresponding to that the k-value are strongly increasing, as does the leakage current density. FTIR spectra show a shift within Si-O-Si backbone and Si-CH₃ and CH₃ bonds are vanishing, while OH groups are adsorbed, additionally leading to higher k-value and leakage currents. Both materials show very good gap-fill properties, filling features with aspect ratios up to 5 or 10 and Aluminium covered structures without any visible defects.     

Evaluation of a PECVD advanced barrier (k = 3.7) for 32 nm CMOS technology and below

An advanced dielectric barrier proposed for sub-45 nm CMOS technology nodes is firstly characterized on 300 mm full sheet wafers. The barrier is a bi-layer deposited by PECVD. The copper diffusion barrier property is ensured by a depositing dense initiation layer with the efficiency of a standard SiCN barrier (k = 5.0). The top layer, thicker, with lower density, enables the decrease of the barrier k-value to 3.66 and plays the role of etch stop layer. Combined with a PECVD porous a-SiOC:H dielectric (k-value = 2.5), the advanced dielectric barrier is successfully integrated in a C65 dual damascene architecture reaching a 3% gain in RC. A high via chain resistance yield is evidence of good via opening. Finally, the advanced barrier shows the same electromigration performance than the standard SiCN barrier.