Thermally annealed Ni/n-GaAs(Si)/In Schottky barrier diodes

We have identically prepared as many as eight Ni/n-GaAs/In Schottky barrier diodes (SBDs) using an n-type GaAs substrate with a doping density of about 7.3 × 10¹⁵ cm⁻³. The thermal stability of the Ni/n-GaAs/In Schottky diodes has been investigated by means of current-voltage (I-V) techniques after annealed for 1 min in N₂ atmosphere from 200 to 700 °C. For Ni/n-GaAs/In SBDs, the Schottky barrier height Φ_b and ideality factor n values range from 0.853 ± 0.012 eV and 1.061 ± 0.007 (for as-deposited sample) to 0.785 ± 0.002 eV and 1.209 ± 0.005 (for 600 °C annealing). The ideality factor values remained about unchanged up to 400 °C annealing. The I-V characteristics of the devices deteriorated at 700 °C annealing.     

Annealing temperature effect on electrical and structural properties of Cu/Au Schottky contacts to n-type GaN

Schottky contacts were fabricated on n-type GaN using a Cu/Au metallization scheme, and the electrical and structural properties have been investigated as a function of annealing temperature by current-voltage (I-V), capacitance-voltage (C-V), Auger electron spectroscopy (AES) and X-ray diffraction (XRD) measurements. The extracted Schottky barrier height of the as-deposited contact was found to be 0.69 eV (I-V) and 0.77 eV (C-V), respectively. However, the Schottky barrier height of the Cu/Au contact slightly increases to 0.77 eV (I-V) and 1.18 eV (C-V) when the contact was annealed at 300 °C for 1 min. It is shown that the Schottky barrier height decreases to 0.73 eV (I-V) and 0.99 eV (C-V), 0.56 eV (I-V) and 0.87 eV (C-V) after annealing at 400 °C and 500 °C for 1 min in N₂ atmosphere. Norde method was also used to extract the barrier height of Cu/Au contacts and the values are 0.69 eV for the as-deposited, 0.76 eV at 300 °C, 0.71 eV at 400 °C and 0.56 eV at 500 °C which are in good agreement with those obtained by the I-V method. Based on Auger electron spectroscopy and X-ray diffraction results, the formation of nitride phases at the Cu/Au/n-GaN interface could be the reason for the degradation of Schottky barrier height upon annealing at 500 °C.     

The electrical characteristics of Sn/methyl-red/p-type Si/Al contacts

The junction characteristics of the organic compound methyl-red film (2-[4-(dimethylamino)phenylazo]benzoic acid) on a p-type Si substrate have been studied. The current-voltage characteristics of the device have rectifying behavior with a potential barrier formed at the interface. The barrier height and ideality factor values of 0.73 eV and 3.22 for the structure have been obtained from the forward bias current-voltage (I-V) characteristics. The interface state energy distribution and their relaxation time have ranged from 1.68 × 10¹² cm⁻² eV⁻¹ and 1.68 × 10⁻³ s in (0.73-E_v) eV to 1.80 × 10¹² cm⁻² eV⁻¹ and 5.29 × 10⁻⁵ s in (0.43-E_v) eV, respectively, from the forward bias capacitance-frequency and conductance-frequency characteristics. Furthermore, the relaxation time of the interface states shows an exponential rise with bias from (0.43-E_v) eV towards (0.73-E_v) eV.     

Effect of series resistance on the electrical characteristics and interface state energy distributions of Sn/p-Si (MS) Schottky diodes

In this study, electrical characteristics of the Sn/p-type Si (MS) Schottky diodes have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height obtained from C-V measurement is higher than obtained from I-V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure Sn/p-Si interface. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (Φ_b) and the series resistance (R_S). The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions. In addition, the interface-state density (N_SS) as a function of energy distribution (E_SS-E_V) was extracted from the forward-bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_b) and series resistance (R_S) for the Schottky diodes. While the interface-state density (N_SS) calculated without taking into account series resistance (R_S) has increased exponentially with bias from 4.235 × 10¹² cm⁻²eV⁻¹ in (E_SS - 0.62) eV to 2.371 × 10¹³ cm⁻²eV⁻¹ in (E_SS - 0.39) eV of p-Si, the N_SS obtained taking into account the series resistance has increased exponentially with bias from of 4.235 × 10¹² to 1.671 × 10¹³ cm⁻²eV⁻¹ in the same interval. This behaviour is attributed to the passivation of the p-doped Si surface with the presence of thin interfacial insulator layer between the metal and semiconductor.     

Molybdenum and low-temperature annealing of a silicon power P-i-N diode

High-power P⁺P-N-N⁺ diodes (V_RRM = 2.5 kV, I_FAV = 150 A) with sputtered Mo layer at anode were annealed in the range 550-800 °C with and without the presence of radiation defects from helium implantation (10 MeV, 1 × 10¹² cm⁻²). The devices were characterized using DLTS, spreading resistance, OCVD lifetime, leakage current, forward voltage drop and reverse recovery measurements. The diffusion of Mo from the 50 nm thick surface layer was not registered even after 4 h between 550 and 800 °C in a rough vacuum. The DLTS confirms the existence of hole deep levels H1 and H2 in the He implanted devices with the Mo anode layer. Similar levels have been already found in the devices with Pt and Pd anode layers, but with different annealing behavior between 600 and 700 °C. Contrary to that of the Pt and Pd, no radiation enhanced diffusion was found from the 50 nm thick Mo surface layer in a rough vacuum.     

The interface states analysis of the MIS structure as a function of frequency

The energy distribution of interface states (N_ss) and their relaxation time (τ) were of the fabricated the Al/SiO₂/p-Si (MIS) structures were calculated using the forward bias current-voltage (I-V), capacitance-frequency (C-f) and conductance-frequency (G-f) measurements. Typical ln[I/(1 − exp(−qV/kT)] versus V characteristics of MIS structure under forward bias show one linear region. From this region, the slope and the intercept of this plot on the current axis allow to determine the ideality factor (n), the barrier height (Φ_b) and the saturation current (I_S) evaluated to 1.32, 0.77 eV and 3.05 × 10⁻⁹ A, respectively. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer at metal-semiconductor interface, the interface states and barrier inhomogeneity of the device. The energy distribution of interface states (N_ss) and their relaxation time (τ) have been determined in the energy range from (0.37 − E_v) to (0.57 − E_v) eV. It has been seen that the N_ss has almost an exponential rise with bias from the mid gap toward the top of valance band. In contrary to the N_ss, the relaxation time (τ) shows a slow exponential rise with bias from the top of the E_v towards the mid gap energy of semiconductor. The values of N_ss and τ change from 6.91 × 10¹³ to 9.92 × 10¹³ eV⁻¹ cm⁻² and 6.31 × 10⁻⁴ to 0.63 × 10⁻⁴ s, respectively.     

Influence of rapid thermal annealing temperature on structure and electrical properties of high permittivity HfTiO thin film used in MOSFET

HfTiO thin films were prepared by r.f. magnetron co-sputtering on Si substrate. To improve the electrical properties, HfTiO thin films were post heated by rapid thermal annealing (RTA) at 400 °C, 500 °C, 600 °C and 700 °C in nitrogen. It was found that the film is amorphous below 700 °C and at 700 °C monoclinic phase HfO₂ has occurred. With the increase of the annealing temperature, the film becomes denser and the refractive index increases. By electrical measurements, we found at 500 °C annealed condition, the film has the best electrical property with the largest dielectric constant of 44.0 and the lowest leakage current of 1.81 × 10⁻⁷ A/cm², which mainly corresponds to the improved microstructure of HfTiO thin film. Using the film annealed at 500 °C as the replacement of SiO₂ dielectric layer in MOSFET, combining with TiAlN metal electrode, a 10 μm gate-length MOSFET fabricated by three-step photolithography processes. From the transfer (I_DS–V_G) and output (I_DS–V_DS) characteristics, it shows a good transistor performance with a threshold voltage (V_th) of 1.6 V, a maximum drain current (I_ds) of 9 × 10⁻⁴ A, and a maximum transconductance (G_m) of 2.2 × 10⁻⁵ S.     

Al contacts to nanoroughened p-GaN

Nanoroughening of a p-GaN surface using nanoscale Ni islands as an etch mask was utilized to investigate the feasibility for the flip-chip configuration light-emitting diodes (LEDs) using an Al-based reflector. Improved ohmic characteristics were found for the nanoroughened sample. A specific contact resistivity of 8.9×10⁻² Ω cm² and a reflectance of 82% at 460 nm were measured for the nanoroughened Al contact. The Schottky barrier heights were decreased from 0.81 eV (I-V) and 0.84 eV (Norde) for the Al contact to 0.70 eV (I-V) and 0.69 eV (Norde) for the nanoroughened Al contact. The barrier height reduction may be attributed to enhanced tunneling and the increased contact area due to the nanoroughening. This work suggests that the ohmic contact characteristics and the light extraction efficiency may be improved further with a well-defined nanopatterned p-GaN layer.     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.     

Low gate interface traps AlGaN/GaN HEMTs using a lattice matched ZrZnO transparent gate design

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) using a radio-frequency magnetron sputtered ZrZnO transparent oxide layer as a gate insulator are investigated and compared with traditional GaN HEMTs. A negligible hysteresis voltage shift in the C–V curves is seen, from 0.09 V to 0.36 V, as the thickness of ZrZnO films increases. The composition of ZrZnO at different annealing temperatures is observed using X-ray photoelectron spectroscopy (XPS). The ZrZnO thin film achieves good thermal stability after 600 °C, 700 °C and 800 °C post-deposition annealing (PDA) because of its high binding energy. Based on the interface trap density analysis, D_it has a value of 2.663 × 10¹² cm⁻²/eV for 10-nm-thick ZrZnO-gate HEMTs and demonstrates better interlayer characteristics, which results in a better slopes for the I_ds degradation (5.75 × 10⁻¹ mA/mm K⁻¹) for operation from 77 K to 300 K. The 10-nm-thick ZrZnO-gate device also exhibits a flat and a stable 1/f noise, as V_GS–V_th, and at various operating temperatures. Therefore, ZrZnO has good potential for use as the transparent film for a gate insulator that improves the GaN-based FET threshold voltage and improves the number of surface defects at various operating temperatures.     

The electrical characteristics of Al/p-InP Schottky contacts

In this study, it has been investigated the electrical characteristics of identically prepared Al/p-InP Schottky diodes. The barrier heights (BHs) and ideality factors of all devices have been calculated from the electrical characteristics. Although the diodes were all identically prepared, there was a diode-to-diode variation: the effective barrier heights ranged from 0.83 ± 0.01 to 0.87 ± 0.01 eV, and the ideality factors ranged from 1.13 ± 0.02 to 1.21 ± 0.02. The barrier height vs. ideality factor plot has been plotted for the devices. Lateral homogeneous BH was calculated as a value of 0.86 eV from the observed linear correlation between BH and ideality factor, which can be explained by laterally inhomogeneities of BHs. The values of barrier height and free carrier concentration yielded from the reverse bias capacitance-voltage (C-V) measurements ranged from 0.86 ± 0.04 to 1.00 ± 0.04 eV and from (3.47 ± 0.39) × 10¹⁷ to (4.90 ± 0.39) × 10¹⁷ cm⁻³, respectively. The mean barrier height and mean acceptor doping concentration from C-V characteristics have been calculated as 0.91 eV and 3.99 × 10¹⁷ cm⁻³, respectively.     

The analysis of I-V characteristics of Schottky diodes by thermionic emission with a Gaussian distribution of barrier height

The current-voltage (I-V) characteristics of Al/p-Si Schottky barrier diode (SBD) with native insulator layer were measured in the temperature range of 178-440 K. The estimated zero-bias barrier height Φ_B0 and the ideality factor n assuming thermionic emission (TE) theory have shown strong temperature dependence. Evaluation of the forward I-V data have revealed an increase of zero-bias barrier height Φ_B0 but the decrease of ideality factor n with the increase in temperature. The experimental and theoretical results of the tunneling current parameter E_o against kT/q were plotted to determine predominant current-transport mechanism. But the experimental results were found to be disagreement with the theoretical results of the pure TE, the thermionic-field emission (TFE) and the field emission (FE) theories. The conventional Richardson plot has exhibited non-linearity below 240 K with the linear portion corresponding to the activation energy of 0.085 eV and Richardson constant (A^*) value of 2.48 × 10⁻⁹ A cm⁻² K⁻² which is much lower than the known value of 32 A cm⁻² K⁻² for holes in p-type Si. Such behaviours were attributed to Schottky barrier inhomogeneities by assuming a Gaussian distribution of barrier heights (BHs) due to barrier height inhomogeneities that prevail at interface. Thus, the modified ln(I_o/T²) − q2σo2/2k²T² vs q/kT has plotted. Then A^* was calculated as 38.79 A cm⁻² K⁻² without using the temperature coefficient of the barrier height. This value of the Richardson constant 38.79 A cm⁻² K⁻² is very close to the theoretical value of 32 A K⁻² cm⁻² for p-type Si. Hence, it has been concluded that the temperature dependence of the forward I-V characteristics of the Al/p-Si Schottky barrier diodes with native insulator layer can be successfully explained on the basis of TE mechanism with a Gaussian distribution of the barrier heights.     

Interface control of conventional n-type silicon/metal by n-channel organic semiconductor

The rectifying and interface state density properties of n-Si/violanthrone-79/Au metal-diode have been investigated by current-voltage and capacitance-conductance-frequency methods. The ideality factor, barrier height and average series resistance of the diode were found to be 2.07, 0.81 eV and 5.04 kΩ respectively. At higher voltages, the organic layer contributes to I-V characteristics of the diode due to space-charge injection into the organic semiconductor layer and the trapped-charge-limited current mechanism is dominant mechanism for the diode. The barrier height obtained from C-V measurement is lower than the barrier height obtained I-V measurement and the organic layer creates an excess physical barrier for the diode. The interface state density of the diode was found to be 1.70 × 10¹¹ eV⁻¹ cm⁻² at 0.2 V and 1.72 × 10¹¹ eV⁻¹ cm⁻² at 0.4 V.The obtained electronic parameters indicate that the organic layer provides the conventional n-type silicon/metal interface control option.     

Laterally inhomogeneous barrier analysis of identically prepared Cd/CdS/n-Si/Au-Sb structures by SILAR method

In this study, CdS thin films have been deposited on n-Si substrate using a successive ionic layer adsorption and reaction (SILAR) method at room temperature. Structural properties have been investigated by means of X-ray diffraction (XRD) and scanning electron microscopy (SEM) measurements. The XRD and SEM investigations show that films are covered well, polycrystalline structure and good crystallinity levels. The Cd/CdS/n-Si/Au-Sb structures (28 dots) have been identically prepared by the SILAR method. The effective barrier heights and ideality factors of these structures have been obtained from forward bias current-voltage (I-V) and reverse bias capacitance voltage (C-V) characteristics. The barrier height (BH) for the Cd/CdS/n-Si/Au-Sb structure calculated from the I-V characteristics have ranged from 0.664 eV to 0.710 eV, and the ideality factor from 1.190 to 1.400. Lateral homogeneous barrier height has been determined approximately 0.719 eV from the experimental linear relationship between BHs and ideality factors. The experimental BH and ideality factor distributions obtained from the I-V characteristics have been fitted by a Gaussian function, and their means of values have been found to be (0.683 ± 0.01) eV and (1.287 ± 0.05), respectively. The barrier height values obtained from the reverse bias C⁻²-V characteristics have ranged from 0.720 eV to 0.865 eV and statistical analysis yields the mean (0.759 ± 0.02) eV. Additionally, a doping concentration obtained from C⁻²-V characteristics has been calculated (8.55 ± 1.62) × 10¹⁴ cm⁻³.     

Fabrication and characterization of p-n junctions based on ZnO and CuPc

p-n Junctions based on zinc oxide (ZnO) and copper-phthalocyanine (CuPc) were fabricated using pulsed laser deposition and thermal evaporator techniques, respectively. Current-voltage (I-V) characteristics of the ZnO-CuPc junction showed rectifying behavior. Various junction parameters such as barrier height and ideality factor were calculated using I-V data and observed to be 0.63 ± 0.02 eV and 4.0 ± 0.3, respectively. Cheung and Norde’s method were used to compare the junction parameters obtained by I-V characteristics.     

Thin titanium oxide films deposited by e-beam evaporation with additional rapid thermal oxidation and annealing for ISFET applications

Titanium oxide (TiO₂) has been extensively applied in the medical area due to its proved biocompatibility with human cells [1]. This work presents the characterization of titanium oxide thin films as a potential dielectric to be applied in ion sensitive field-effect transistors. The films were obtained by rapid thermal oxidation and annealing (at 300, 600, 960 and 1200 °C) of thin titanium films of different thicknesses (5 nm, 10 nm and 20 nm) deposited by e-beam evaporation on silicon wafers. These films were analyzed as-deposited and after annealing in forming gas for 25 min by Ellipsometry, Fourier Transform Infrared Spectroscopy (FTIR), Raman Spectroscopy (RAMAN), Atomic Force Microscopy (AFM), Rutherford Backscattering Spectroscopy (RBS) and Ti-K edge X-ray Absorption Near Edge Structure (XANES). Thin film thickness, roughness, surface grain sizes, refractive indexes and oxygen concentration depend on the oxidation and annealing temperature. Structural characterization showed mainly presence of the crystalline rutile phase, however, other oxides such Ti₂O₃, an interfacial SiO₂ layer between the dielectric and the substrate and the anatase crystalline phase of TiO₂ films were also identified. Electrical characteristics were obtained by means of I-V and C-V measured curves of Al/Si/TiO_x/Al capacitors. These curves showed that the films had high dielectric constants between 12 and 33, interface charge density of about 10¹⁰/cm² and leakage current density between 1 and 10⁻⁴ A/cm². Field-effect transistors were fabricated in order to analyze I_D x V_DS and log I_D × Bias curves. Early voltage value of −1629 V, R_OUT value of 215 MΩ and slope of 100 mV/dec were determined for the 20 nm TiO_x film thermally treated at 960 °C.     

Studies of defect states of ZnO thin films under different annealing conditions

ZnO thin films were grown by the pulsed laser deposition technique on c-plane sapphire substrates at a substrate temperature of 500 °C with 1×10⁻⁴ Torr ambient gas. After the deposition process, ZnO thin films were annealed at 1000 °C for 5 min under N₂ or O₂ ambient gas, respectively. In the X-ray patterns, the (0 0 2) peak of the annealed sample was shifted from that of the as-grown sample, which indicates a reduced lattice constant of about 1%. Even though the X-ray diffraction patterns in the samples annealed under O₂ and N₂ annealing gases were almost the same, photoluminescence spectra showed the generation of a shallow level with a few meV, and deep-level states were generated at E_v+0.594 eV. In addition, a defect state appeared at E_c−0.607 eV, which originated from hydrogen plasma irradiation on the ZnO sample.     

Study of deep level defect behavior in undoped n-InP (1 0 0) after rapid thermal annealing

The effects of rapid thermal annealing on deep level defects in the undoped n-type InP with Ru as Schottky contact metal have been characterized using deep level transient spectroscopy (DLTS). It is observed that the as-deposited sample exhibit two deep levels with activation energies of 0.66 and 0.89 eV. For the samples annealed at 300 °C and 400 °C, a deep level is identified with activation energies 0.89 and 0.70 eV, respectively below the conduction band. When the sample is annealed at 500 °C, three deep levels are observed with activation energies 0.25, 0.32 and 0.66 eV. Annealing of the sample at 300 °C, orders the lattice of as-grown material by suppressing the defect 0.66 eV (A1) which is found in the as-deposited sample. The trap concentration of the 0.89 eV deep levels is found to be increased with annealing temperature. The deep level 0.32 eV may be due to the lattice defect by thermal damage during rapid thermal annealing process such as vacancies, interstitials and its complexes, indicating the damage of the sample after annealing at 500 °C. The defects observed in all the samples are possibly due to the creation of phosphorous vacancy or phosphorous antisite.     

Electrical characterisation of SiON/n-Si structures for MOS VLSI electronics

In the present work, we examine the properties of SiON films grown on Si substrates by CVD in order to investigate their suitability as potential materials in replacing SiO₂ in metal-oxide-semiconductor (MOS) devices. Suitable metallization created MOS devices and electrical characterisation took place in order to identify their electrical properties. Electrical measurements included current-voltage (I-V), capacitance-conductance-voltage (C-V) measurements and admittance spectroscopy (Y−ω) allowing determination of the bulk charges and the dielectric response of the films. The analysis of the data also took into account the presence of traps at the Si/SiON interface calculated by a fast conductance technique. The interface states density was of the order of 10¹² eV⁻¹ cm⁻². The dielectric constant was found to lie between 16 and 4.5 and the corresponding bulk trapped charges were found between 8 and 113 μCb cm⁻². Post deposition annealing altered these values showing an improvement of the device behaviour. A short explanation of the above is also provided.     

Four-point probe characterization of 4H silicon carbide

We report on four-point probe measurements on SiC wafers as such measurements give erratic data. Current-voltage measurements on n-type SiC wafers doped to 3 × 10¹⁸ cm⁻³ are non-linear and single probe I-V measurements are symmetrical for positive and negative voltages. For comparison, similar measurements of p-type Si doped to 5 × 10¹⁴ cm⁻³ gave linear I-V, well-defined sheet resistance and the single probe I-V curves were asymmetrical indicating typical Schottky diode behavior. We believe that the reason for the non-linearity in four-point probe measurements on SiC is the high contact resistance. Calculations predict the contact resistance of SiC to be approximately 10¹² Ω which is of the order of the input resistance of the voltmeter in our four-point probe measurements. There was almost no change in two-probe I-V curves when the spacing between the probes was changed from 1 mm to 2 cm, further supporting the idea that the I-V characteristics are dominated by the contact resistance.