Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement

Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Q_cp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.     

Gentle FUSI NiSi metal gate process for high-k dielectric screening

In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

CHC degradation of strained devices based on SiON and high-k gate dielectric materials

A comparison between the Channel Hot-Carrier (CHC) degradation on strained pMOSFETs with SiGe source/drain (S/D) based on different gate dielectric materials, as SiON or HfSiON, has been done. The influence of the device channel orientation, channel length and temperature on the CHC damage has been studied.     

A nanoanalytical investigation of elemental distributions in high-k dielectric gate stacks on silicon

Two high-k gate stacks with the structure Si/SiO₂/HfO₂/TiN/poly-Si are characterised using nanoanalytical electron microscopy. The effect of two key changes to the processing steps during the fabrication of the stacks is investigated. Electron energy-loss spectroscopy is used to show that the TiN layer has a very similar composition whether it is deposited by PVD or ALD. Spectrum imaging in the electron microscope was used to profile the distribution of elements across the layers in the stack. It was found that when the anneal after HfO₂ deposition is carried out in a NH₃ atmosphere instead of an O₂ atmosphere, there is diffusion of N into the SiO₂ and HfO₂ layers. There is also significant intermixing of the layers at the interfaces for both wafers.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

High-quality high-k HfON formed with plasma jet assisted PVD process and application as tunnel dielectric for flash memories

We demonstrate low-trap-density HfON film made by the molecular-atomic deposition (MAD) technique, which is an Ar/N₂ plasma jet assisted physical vapor deposition process. This high-k HfON can be deposited on top of the nearly trap-free MAD-Si₃N₄ to form a single-side crested tunnel barrier. The Al/(HfON-Si₃N₄)/Si capacitor structure with HfON/Si₃N₄ stack as the tunnel barrier demonstrates steeper I-V slope than that of a single layer SiO₂ with the same EOT, and is readily applicable to improve the programming speed and data retention of flash memories.     

Performance of current mirror with high-k gate dielectrics

This work compares the performance of the basic current mirror topology by using two different materials for gate dielectrics, the conventional SiON and an Hf-based high-k dielectrics. The impact of gate leakage and of channel length modulation on the basic current mirror operation is described. It is shown that in the case of SiON gate dielectrics with an equivalent oxide thickness (EOT) of 1.4 nm, it is not possible to find a value for the channel length which allows a good trade-off to be obtained while minimizing the gate leakage and reducing the channel length modulation. On the other hand, the study demonstrates that in the case of HfSiON gate dielectrics with similar EOT, appropriate L values can be found obtaining very high output impedance current sources with reduced power consumption owing to low leakage and most of all with better parameter predictability.     

Carrier transport mechanism in La-incorporated high-k dielectric/metal gate stack MOSFETs

In this paper, carrier transport mechanism of MOSFETs with HfLaSiON was analyzed. It was shown that gate current is consisted of Schottky emission, Frenkel-Poole (F-P) emission and Fowler-Nordheim (F-N) tunneling components. Schottky barrier height is calculated to be 0.829 eV from Schottky emission model. Fowler-Nordheim tunneling barrier height was 0.941 eV at high electric field regions and the trap energy level extracted using Frenkel-Poole emission model was 0.907 eV. From the deviation of weak temperature dependence for gate leakage current at low electric field region, TAT mechanism is also considered.     

Resistive switching effects of HfO2 high-k dielectric

Resistive switching behavior of HfO₂ high-k dielectric has been studied as a promising candidate for emerging non-volatile memory technology. The low resistance ON state and high resistance OFF state can be reversibly altered under a low SET/RESET voltage of ±3 V. The memory device shows stable retention behavior with the resistance ratio between both states maintained greater than 103. The bipolar nature of the voltage-induced hysteretic switching properties suggests changes in film conductivity related to the formation and removal of electronically conducting paths due to the presence of oxygen vacancies induced by the applied electric field. The effect of annealing on the switching behavior was related to changes in compositional and structural properties of the film. A transition from bipolar to unipolar switching behavior was observed upon O₂ annealing which could be related to different natures of defect introduced in the film which changes the film switching parameters. The HfO₂ resistive switching device offers a promising potential for high density and low power memory application with the ease of processing integration.     

Rare earth-based high-k materials for non-volatile memory applications

A study of a La-based high-k oxide to be employed as active dielectric in future scaled memory devices is presented. The focus will be held on La_xZr_1−xO_2−δ (x = 0.25) compound. In order to allow the integration of this material, its chemical interaction with an Al₂O₃ cap layer has been studied. Moreover, the electrical characteristics of these materials have been evaluated integrating them in capacitor structures. The rare earth-based ternary oxide is demonstrated to be a promising candidate for future non-volatile memory devices based on charge trapping structure.     

Evaluation of HfAlO high-k materials for control dielectric applications in non-volatile memories

In this paper, we evaluate the potentiality of hafnium aluminium oxide (HfAlO) high-k materials for control dielectric application in non-volatile memories. We analyze the electrical properties (conduction and parasitic trapping) of HfAlO single layers and SiO₂/HfAlO/SiO₂ triple layer stacks as a function of the HfAlO thickness and Hf:Al ratio. A particular attention is given to the electrical behaviour of the samples at high temperature, up to 250 °C. Experimental results obtained on silicon nanocrystal memories demonstrate the high advantage of HfAlO based control dielectrics on the memory performances for Fowler-Nordheim operation. Then an analytical model is presented, to simulate the program erase characteristics in the transient regime and at saturation, depending on the high-k control dielectric properties. A very good agreement is obtained between the experimental data and the simulation results.     

Characterization of low-k SiOCH dielectric for 45 nm technology and link between the dominant leakage path and the breakdown localization

Electrical characterizations have been performed on porous low-k SiOCH dielectric used in the 45 nm technology. The present paper demonstrates that the conduction follows the Poole-Frenkel (PF) mechanism at medium and high fields. The apparent deviation from the PF mechanism at high field is explained by the trapping phenomenon due to the large amount of defects in the dielectric. This trapping deforms the band diagram and lowers the electron injection within the dielectric. A study of two key process steps is also performed and shows that the dominant conduction mechanism localization (bulk versus interface) is not necessarily at the origin of the breakdown mechanism.     

Process damage-free damascene metal gate technology for gentle integration of epitaxially grown high-k

This paper presents the first successful attempt to integrate crystalline high-k gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness (EOT) down to 1.9 nm are discussed and compared with devices with rare-earth gate dielectrics fabricated previously in a conventional CMOS process.     

Effect of thin Si insertion at metal gate/high-k interface on electrical characteristics of MOS device with La2O3

The effect of a thin Si layer insertion at W/La₂O₃ interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La₂O₃ layer by forming an amorphous La-silicate layer at the W/La₂O₃ interface. In addition, positive shifts in V_fb and V_th caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La₂O₃ dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high E_eff of 1 MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit.     

Effect of interfacial fluorination on the electrical properties of the inter-poly high-k dielectrics

In this paper, the reliabilities and insulating characteristics of the fluorinated aluminum oxide (Al₂O₃) and hafnium oxide (HfO₂) inter-poly dielectric (IPD) are studied. Interface fluorine passivation has been demonstrated in terminating dangling bonds and oxygen vacancies, reducing interfacial re-oxidation and smoothing interface roughness, and diminishing trap densities. Compared with the IPDs without fluorine incorporation, the results clearly indicate that fluorine incorporation process is effective to improve the insulating characteristics of both the Al₂O₃ and HfO₂ IPDs. Moreover, fluorine incorporation will also improve the dielectric quality of the interfacial layer. Although HfO₂ possesses higher dielectric constant to increase the gate coupling ratio, the results also demonstrate that fluorination of the Al₂O₃ dielectric is more effective to promote the IPD characteristics than fluorination of the HfO₂ dielectric. For future stack-gate flash memory application, the fluorinated Al₂O₃ IPD undoubtedly possesses higher potential to replace current ONO IPD than the fluorinated HfO₂ IPD due to superior insulating properties.     

32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k = 2.3

A 32 nm node BEOL integration scheme is presented with 100 nm metal pitch at local and intermediate levels and 50 nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32 nm RC performance specifications, extreme low-k (ELK) porous SiOCH k = 2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k = 2.3 is investigated using a multi-level metallization test vehicle in a 45 nm mature generation.     

Density functional theory study of first-layer adsorption of ZrO2 and HfO2 on Ge(1 0 0)

Density functional theory was used to performed a survey of transition metal oxide (MO₂ = ZrO₂, HfO₂) ordered molecular adsorbate bonding configurations on the Ge(1 0 0)-4 × 2 surface. Surface binding geometries of metal-down (O-M-Ge) and oxygen-down (M-O-Ge) were considered, including both adsorbate and displacement geometries of M-O-Ge. Calculated enthalpies of adsorption show that bonding geometries with metal-Ge bonds (O-M-Ge) are essentially degenerate with oxygen-Ge bonding (M-O-Ge). Calculated electronic structures indicate that adsorbate surface bonding geometries of the form O-M-Ge tend to create a metallic interfaces, while M-O-Ge geometries produce, in general, much more favorable electronic structures. Hydrogen passivation of both oxygen and metal dangling bonds was found to improve the electronic structure of both types of MO₂ adsorbate systems, and induced the opening of true semiconducting band gaps for the adsorbate-type M-O-Ge geometries. Shifts observed in the DOS minima for both O-M-Ge and M-O-Ge adsorbate geometries are consistent with surface band bending induced by the adsorbate films, where such band bending extends much further into the Ge substrate than can be modeled by the Ge slabs used in this work.     

Microstructure and stress in high-k Hf-Y-O thin films

We investigated the microstructure and the stress of high-k Hf-Y-O thin films deposited by atomic layer deposition (ALD). These hafnium oxide based films with a thickness of 5-60 nm stabilized in crystal structure with yttrium oxide by alternating the Hf- or Y-containing metal precursor during deposition. The microstructure was investigated by XRD and TEM in dependence of substrate and deposition temperature. The film stress was monitored during thermal cycles up to 500 °C using the substrate curvature method on (1 0 0)-Si wafer material with or without 10 nm TiN bottom electrode as well as on fused silica. It was observed that crystallinity and phases are depending on deposition temperature and film thickness. During thermal treatment the films crystallize depending on deposition temperature, yttrium content and substrate material at different temperatures. Crystallization of the films depends strongly on yttrium content. The highest reduction of 720 MPa was observed for films deposited with a Hf:Y cycle ratio of 10:1 where 6.2% of all metal atoms are replaced by yttrium. These Hf-Y-O films also show the highest k-value of 29 and have the smallest thermal expansion coefficient mismatch to TiN electrodes. Therefore we conclude that Hf-Y-O films are candidates for application in next generations of microelectronic MIM-capacitor devices or metal gate transistor technology.     

Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON

For the first time, we present a comparative study on HfLaSiON and HfLaON gate dielectric with an equivalent oxide thickness (EOT) of 0.8 nm (T_inv = 1.2 nm). A detailed DC analysis of I_on vs. I_off shows HfLaON performs somewhat better than HfLaSiON. However, positive bias temperature instability (PBTI) lifetime of HfLaSiON is higher than HfLaON by about 2 orders of magnitude. On the other hand, hot carrier stress lifetime for HfLaSiON was similar to that of HfLaON. From the activation energy and U-trap, we found that the cause of different threshold voltage (V_T) shifts under PBT stress and detrapping was originated from stable electron traps induced by different charge trapping rates.