Compact CMOS Baluns for the 4–10 GHz Band Applications

In this paper, we proposed two baluns, a compact balun and a compact balun with imbalance compensation; both are implemented using the one-poly six-metal (1P6M) 0.18 μ m CMOS process. Both baluns have good performance from 4 to 10 GHz, and consume less silicon area due to their compact structure. The self-resonant frequency is increased by properly selecting metal layer for each spiral winding. The compact balun has a magnitude imbalance of 1 dB and a phase imbalance of 4.6 degree from 4 to 10 GHz. With the imbalance compensation, the balun has a magnitude imbalance of 0.6 dB and a phase imbalance of 1.1 degree from 4–10 GHz. Much better results have been achieved for the compact balun with our proposed imbalance compensation method. Both baluns can be used to perform both single-ended/differential and differential/single-ended conversions in different configurations.     

Novel miniaturised wideband baluns for MIC and MMIC applications

Very compact novel planar broadband baluns are described. Each balun consists of two Lange couplers. Less than 0.3 dB and 2.5 degrees for the amplitude and phase balances, respectively, have been measured over the 1.0-2.2 GHz bandwidth for a microstrip balun. As compared with other reported baluns, these baluns are simpler, more compact, easier to design, and fabricated on only one side of the substrate. They are thus very attractive for microwave integrated circuit (MIC) and monolithic microwave integrated circuit (MMIC) applications.<>     

A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles.     

Design of a wideband multi-standard antenna switch for wireless communication devices

A wideband Low Power Single Pole 6-Throw (SP6T) antenna switch has been designed for GSM/DCS/802.11b mobile standards using a newly improved architecture and fabricated using a pseudomorphic depletion mode 0.18 μm HEMT GaAs process. The switch exhibits less than 1 dB insertion loss and isolation performances from up to 53 dB at 0.8 GHz down to 42 dB at 2.5 GHz. The circuit DC power consumption is less than 500 μW in full power transmission condition and makes it suitable for use in mobile terminals like mobile phones or PDAs. The paper presents simulation results validated by experimental measurements on an IC prototype.     

Clock buffer with duty cycle corrector

A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as input clock. It corrects the input duty cycle of 10-90% for generated 50% duty cycle of output clock with error less than 0.9%. Moreover, it enhances the input clock signal driving ability and keeps the same duty cycle as input clock within range from 20% to 80% with a maximum duty error of 0.5%. The proposed circuit operation frequency range is from 100 MHz to 1 GHz. The proposed circuit has been fabricated in a 0.18 μm CMOS technology.     

Optimum Design of Wideband Compensated and Uncompensated Marchand Baluns With Step Transformers

This paper presents a design approach for wideband compensated and uncompensated Marchand baluns with stepped-impedance transformers. In order to obtain an equal-ripple bandpass response, conventional Chebyshev polynomials are modified to compensate the effect of the transfer function's dc poles. Unlike the available microwave filter design approaches, which usually require redundant elements, this approach leads to an optimum design by using the minimum number of equal length transmission line elements. Based on this design approach, both compensated and uncompensated Marchand baluns are studied. It is found that increasing difficulty arises when implementing a large bandwidth balun using the widely adopted compensated balun structure. Hence, the uncompensated balun structure becomes a better choice. To validate the proposed design approach, an uncompensated balun is designed on a standard two-sided printed circuit board. The measured results indicate that a return loss greater than 20 dB can be observed from 1 to 7.5 GHz. The phase imbalance is less than 4° and the amplitude is less than 0.5 dB from dc to 7.2 GHz.      

Analysis and design of wide band Microstrip-line-fed antenna with defected ground structure for Ku band applications

A wide band Microstrip antenna is proposed for Ku band applications with defected ground structure. A circular shape defect is integrated in the ground plane. A novel equivalent circuit model is proposed for Microstrip patch antenna with defected ground structure. Accurate design equations are presented for the wideband Microstrip antenna and theoretical analysis is done for the proposed structure. The proposed antenna has an impedance bandwidth of 56.67% ranging from 9.8 GHz to 17.55 GHz, which covers Ku-band and partially X-band. The antenna shows good radiation characteristics within the entire band, and has a gain ranging from 5 dBi to 12.08 dBi. Minimum isolation between co-polar and cross-polarization level of 20 dB and 15 dB is achieved in H-plane and E-plane respectively. The simulation of the proposed antenna is done on HFSS v.14, and measured results of fabricated antenna are in good agreement with the theoretical and simulated results.     

Low-Loss and Broadband Asymmetric Broadside-Coupled Balun for Mixer Design in 0.18-$mu{hbox {m}}$ CMOS Technology

This study presents an asymmetric broadside coupled balun with low-loss broadband characteristics for mixer designs. The correlation between balun impedance and a 3D multilayer CMOS structure are discussed and analyzed. Two asymmetric multilayer meander coupled lines are adopted to implement the baluns. Three balanced mixers that comprise three miniature asymmetric broadside coupled Marchand baluns are implemented to demonstrate the applicability to MOS technology. Both a single and dual balun occupy an area of only 0.06 mm². The balun achieves a measured bandwidth of over 120%, an insertion loss of better than 4.1 dB (3 dB for an ideal balun) at the center frequency, an amplitude imbalance of less than 1 dB, and a phase imbalance of less than 5deg from 10 to 60 GHz. The first demonstrated circuit is a Ku-band mixer, which is implemented with a miniaturized balun to reduce the chip area by 80%. This 17-GHz mixer yields a conversion loss of better than 6.8 dB with a chip size of 0.24 mm². The second circuit is a 15-60-GHz broadband single-balanced mixer, which achieves a conversion loss of better than 15 dB and occupies a chip area of 0.24 mm². A three-conductor miniaturized dual balun is then developed for use in the third mixer. This star mixer incorporates two miniature dual baluns to achieve a conversion loss of better than 15 dB from 27 to 54 GHz, and occupies a chip area of 0.34 mm².     

Ultra low power phase detector and phase-locked loop designs and their application as a receiver

In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48 μW power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13 μm CMOS technology. Dissipating 0.26 mW from a 1.2 V supply, the fabricated PLL can track signals between 1.62 and 2.49 GHz. For receiver applications, the energy per bit of the receiver is only 0.26 nJ making it attractive for low power applications including wireless sensor networks.     

A highly miniaturized LTCC dual-band UWB filter using independent transmission zeros and lowpass filters

In this paper, a compact dual-band ultra-wideband (UWB) filter has been newly designed and fabricated for 3.1–4.75 GHz and 6.0–8.5 GHz UWB system applications by embedding all passive lumped elements into low temperature co-fired ceramic (LTCC) substrate. In order to reduce its size/volume and prevent parasitic electromagnetic (EM) coupling between the embedded passive elements, it was newly designed by using a modified 3rd order Chebyshev filter topology and J-inverter transformation technology. Moreover, in order to completely reject the wireless local area network (WLAN) bands of 2.4 GHz and 5.15 GHz, an independent transmission zeros technology was applied. For forming the higher passband, lowpass filters were also applied with two LC resonant circuits by using roll-off characteristics by independent transmission zeros. The measured insertion losses in the lower and upper passbands were better than 2.5 and 2.3 dB, respectively. Return loss and group delay were better than 8 dB and 0.61 ns, respectively in all the passbands. Independent transmission zeros that occurred at 5.17 and 5.42 GHz provided suppression of 22 dB at the WLAN band. The size/volume of the fabricated LTCC dual-band UWB filter was 3.65×2.35×0.65 (H) mm³.     

Broadband monolithic passive baluns and monolithic double-balancedmixer

The design and fabrication of four broadband monolithic passive baluns including CPW Marchand, multilayer MS Marchand, planar-transformer and broadside-coupled line baluns are presented. Operational frequencies range from 1.5 GHz to 24 GHz. Maximum relative bandwidths in excess of 3:1 are achieved. Simulated performances using full wave electromagnetic analysis are shown to agree with the measured results. Two accurate equivalent circuit models constructed from either electromagnetic simulated or measured S-parameters are developed for the MS Marchand and transformer baluns making the optimization of baluns and circuit design using the baluns much more efficient. The design of monolithic double-balanced diode mixer using two planar-transformer baluns is also presented. Without DC bias, the mixer shows a minimum conversion loss of 6 dB with the RF at 5 GHz and a LO drive of 15 dBm at 4 GHz. The measured input IP₃ of this mixer is better than 15 dBm over the 4 to 5.75 GHz frequency band     

5–11 GHz CMOS PA with 158.9 ± 41 ps group delay and low power using current-reused technique

This paper proposes the design of a low group delay and low power ultra-wideband (UWB) power amplifier (PA) in 0.18 μm CMOS technology. The PA design employs two stages cascade with inductive peaking technique to provide broad bandwidth characteristic and higher gain while gain flatness can be achieved by connecting inter-stage circuit. A common gate current-reused technique is adopted at the first stage amplifier to achieve good input matching, low group delay and low power. The simulation results show that the proposed PA design has an average gain of 11.5 dB with flatness of ±0.4 dB from 5–11 GHz, while maintaining bandwidth of 4.2–12.3 GHz. An input return loss (S₁₁) less than −10.4 dB and output return loss (S₂₂) less than −9.5 dB, respectively are obtained. The PA design achieves excellent phase linearity (i.e., group delay variation) of ±41 ps and only consuming 17 mW power from 1.2 V supply voltage. A good output 1-dB compression point OP1 dB of 3.7 dBm is obtained. By using this method, the proposed design has low group delay variation and lowest power among the recently reported UWB CMOS PAs applications.     

Integrated linear giga-ohm resistance using current scaling

Integrated grounded resistors of very large value are essential circuit elements for the design of compact filters with very low cut-off frequencies. A typical application of such filters is the rejection of DC voltages in amplifier circuits especially in physiological recording systems exhibiting electrode offset and low-frequency drift. In this letter, the implementation of a giga-ohm resistance is presented using a conventional fixed-gain OTA and a cascade of weak-inversion current scalers. The circuit yields a short design time, small power and area consumption as well as high linearity. A test circuit having an area of 0.011 mm² integrated in 0.35 μm CMOS is presented which yields a 41 Hz cut-off frequency, 1 V input range and less than −52 dB THD when connected to an integrated 1 pF capacitor, making it a suitable solution for the rejection of mains interference and offset in wearable biomedical applications.     

W-band double-balanced down-conversion mixer with marchand baluns in silicon-germanium technology

Presented is a monolithic W-band (75-110 GHz) down-conversion mixer consisting of a double-balanced core, Marchand-type on-chip baluns at inputs, and a two-stage output buffer, fabricated in a 200 GHz f _T SiGe technology. Including the loss for input baluns, this mixer exhibits conversion gains of 14.4 plusmn 2.8 dB and single sideband (SSB) noise figures of less than 19.5 dB across the entire W-band, drawing 28 mA from a 3.3 V supply.     

A dual-gate 2nd/3rd-order subharmonic injection-locked oscillator in GaAs PHEMT

A dual-gate subharmonic injection-locked oscillator (SILO) has been designed and fabricated in 0.5 μm GaAs PHEMT process for millimeter-wave communication applications. Specifically, this study proposes a dual-gate circuit topology to achieve a high-frequency oscillator with a large output signal power. The proposed dual-gate transistor also performs a wideband negative resistance characteristic by which the self-oscillation frequency can easily be determined with a proper resonator. The measured self-oscillation frequency of the proposed SILO is approximately 49 GHz, and the frequency tuning range is adjustable from 48.7 GHz to 49.7 GHz with an output power of 8 dBm. By injecting a 2nd-order (~24.5 GHz) subharmonic signal into the dual-gate SILO, the maximum locking range of 5.6 GHz can be approached at an input power of 11 dBm without any self-oscillation frequency tuning. With changing the input frequency to be a 3rd-order subharmonic injection (~16.3 GHz), an output locking range of 2.9 GHz also can be achieved. The measured phase noises of the output signals from 2nd- and 3rd-order subharmonic injections are −101 and −100 dBc/Hz, respectively, at 100-kHz offset frequency.     

Wideband LC balun transformer using coupled LC resonators embedded into organic substrate

In this paper, wideband LC balun using coupled LC resonator has been newly designed, simulated, and fabricated. The proposed balun has a novel scheme which consists of two pairs of coupled embedded LC resonators which share one resonator with each other. The coupled resonators are applied to provide a precise phase difference of 180° and an identical magnitude between two balanced ports and DC isolation characteristic with impedance transformation. Furthermore, proposed resonators have relatively small inductance values which can be easily embedded into the organic package substrate. In order to reduce the size of embedded capacitors, BTO composite high dielectric film was applied to increase their capacitance densities. The measured results of fabricated wideband balun exhibited an insertion loss of 1.8 dB, a return loss of 10 dB, a phase imbalance of 0.5°, and magnitude imbalance of 0.7 dB at frequency bandwidth of 700 MHz ranged from 1.8 to 2.5 GHz, respectively. They agreed well with the simulated ones. The fabricated balun has a relatively small volume of 2 mm×3.5 mm×0.66 mm (height).     

A VCO-based phase-expanding conversion designed for time-domain data converters

This paper presents the design of a VCO-based phase-expanding converter (PEC) that converts a time residue to improve time resolution for the time-domain data converters. A voltage controlled oscillator, which has multiphase structure, is combined with the multi-layer delay chain to generate quadruple phases, and thus expands the overall resolution. Since the architecture of this converter is flexible for different designs, we propose a 6-bit, 250 MHz PEC using a 16-phase, 1 GHz VCO with quadruple phase expander in this paper. Simulations in a 0.18 μm the CMOS process indicate that the PEC has DNL less than ±0.2 LSB LSB, and INL less than ±0.3 LSB. Furthermore, with the frequency variation from 0.9 GHz to 1.1 GHz, the PEC still has DNL ±0.21 LSB, and INL ±0.29 LSB. Experiment results show that the DNL is 0.52–0.13 LSB and the INL is 0.21–0.66 LSB.     

Design and fabrication of 94 GHz MMIC single balanced resistive mixer without IF balun

In this paper, a 94 GHz microwave monolithic integrated circuit (MMIC) single balanced resistive mixer affording high LO-to-RF isolation was designed without an IF balun. The single balanced resistive mixer, which does not require an external IF balun, was designed using a 0.1 μm InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (HEMT). The designed MMIC single balanced resistive mixer was fabricated using the 0.1 μm MHEMT MMIC process. From the measurement, conversion loss of the single balanced resistive mixer was 14.7 dB at an LO power of 10 dBm. The P_1 dB (1 dB compression point) values of the input and output were 10 dBm and −5.3 dBm, respectively. The LO-to-RF isolation of the single balanced resistive mixer was −35.2 dB at 94.03 GHz. The single balanced resistive mixer in this work provided high LO-to-RF isolation without an IF balun.     

Internally compensated LDO regulator based on the cascoded FVF

In this paper, an internally compensated low dropout (LDO) voltage regulator based on the Flipped Voltage Follower (FVF) is proposed. By means of capacitive coupling and dynamic biasing, the transient response to both load and line variations is enhanced. The proposed circuit has been designed and fabricated in a standard 0.5 µm CMOS technology. Experimental results show that the proposed circuit features a line and a load regulation of 132.04 µV/V and 153.53 µV/mA, respectively. Moreover, the output voltage spikes are kept under 150 mV for a 2 V-to-5 V supply variation and for 1 mA-to-100 mA load variation, both in 1 µs.     

Design and Analysis of Millimeter-Wave Marchand Balun with Interconnected Transmission Line

This paper presents the design and analysis of general baluns of Marchand-type with a transmission line connected between two sections. A series of new expressions of S-parameters are derived for such type of Marchand balun. The relations between the length of interconnected transmission line and the imbalance of Marchand balun are discussed. By using analytical method, a millimeter-wave Marchand balun was designed and simulated by the full-wave electromagnetic software HFSS, and fabricated in 0.15 μm pHEMT GaAs process. The measurement results show that the balun achieves low insertion loss and good balance in the band of 24–40 GHz. The results are in good agreement with the simulated ones. The theoretical analysis is verified.