Integrated electro-thermomechanical analysis of nonuniformly chip-powered microelectronic system

An integrated electrical, fluid flow and thermomechanical analysis is presented to study a product reliability and thermal management solution in an actual or nonuniform chip power distribution of an integrated circuit device in a realistic system application environment. This study aims to improve the existing limitations both on electrothermal analysis where simplified thermal boundary conditions is mostly used and on the current thermal and fluid flow analysis where uniform chip power is widely used to calculate the temperature. In this approach, the localized on-chip power distribution is obtained by using a transistor-level circuit model for simulating the interaction between the macro and functional blocks. A computational fluid dynamics analysis is used to calculate the fluid flow and heat transfer solution with a realistic thermal boundary conditions. To address the ultimate thermal induced mechanical stress and reliability effects on the chip-packaged assembly due to the nonuniform chip power distribution, finite element model is employed for the sequential steady-state heat transfer and mechanical analysis. The results are then discussed and specifically compared with the solutions based on the uniform chip power conditions.     

SCRAP: Sequential circuits reliability analysis program

The recent rapid growth in demand for highly reliable digital circuits has focused attention on tools and techniques we might use to accurately estimate the reliability of a proposed circuit on the basis of failure rate of the utilized technology. Reliability analysis has become an integral part of the system design process, especially for those systems with life-critical applications such as aircrafts and spacecraft flight control. In this paper, we present an algorithm to evaluate the reliability of sequential circuits. This approach called ‘multiple-pass’ combines gate failure probability with the propagated errors to calculate the reliability of every nodes of the circuit in an iterative manner. The proposed approach is used to implement and develop the SCRAP program. It computes the reliability of the sequential circuit based on its standard cell library which can be extended to have larger gates such as D flip-flops. The framework is applied to a subset of sequential benchmark circuits and the observed results demonstrate the accuracy and speed of the proposed technique.     

Floorplanning for low power IC design considering temperature variations

Non-uniformity in thermal profiles of integrated circuits (ICs) is an issue that threatens their performance and reliability. This paper investigates the correlation between the total power consumption and the temperature variations across a chip. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. It is demonstrated that optimizing a floorplan to minimize either the leakage or the peak temperature can lead to a significant increase in the total power consumption. In this paper, the experimental results show that lowering the temperature variations across a chip not only addresses performance degradation and reliability concerns, but also significantly contributes to chip power reduction. In addition, it is found that although uniformity in the thermal profile can be very effective in lowering the total power consumption, the most uniform temperature distribution does not necessarily correspond to the highest power savings. Consequently, for some applications, a 2% deviation from the minimum total power is traded for up to a 25% increase in thermal uniformity. The presented method is implemented for an Alpha 21264 processor running Spec 2000 benchmarks.     

An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects

Due to shrinking feature size and higher transistor count in a single chip in modern fabrication technologies, power consumption and soft error reliability have become two critical challenges which chip designers are facing in new silicon integrated circuits. Recent studies have shown that these issues have compromising effects on each other. Besides, power consumption and reliability significantly vary across workloads and among pieces of a single application which can be exploited to design adaptive runtime fault tolerant and low power systems. These attractions have been exploited in prior studies to design online reconfigurable fault tolerant systems with power management schemes. However, those attempts are driven by complicated simulations and hardly deliver a sense of direction to the designers. To achieve maximum efficiency in terms of power, performance, and reliability in dynamic scaling of voltage and frequency, it is critical to have a simple and accurate reliability model which estimates the value of fault rate considering supply voltage and operating frequency of a circuit. In this paper, we propose an accurate formula for analytic modeling of the soft error rate of a system which can be used to precisely track the reliability of the system under dynamic voltage and frequency adjustments. The experimental results of this paper prove that our proposed model offers precise estimates of reliability in accordance with the results of accurate soft error rate (SER) estimation algorithm for ISCAS85’s benchmark circuits.     

Failure analysis of ULSI circuits using photon emission

A real-time failure analysis technique for ULSI circuits using photon emission is proposed. This technique utilizes a photon detection system combined with a circuit tester. Improved failure detection is achieved because the tester can bias arbitrary blocks in the ULSI chip. Detecting and correct process defects and design errors improves the reliability of the ULSI chip     

Multidisciplinary heat generating logic block placement optimization using genetic algorithm

A multidisciplinary optimization methodology for placement of heat generating semiconductor logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using a genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to determine the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multidisciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. Capabilities of the present methodology are demonstrated by applying it to several standard benchmarks. The multidisciplinary logic block placement optimization results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5 °C, compared to the case in which only the wiring length is minimized.     

An introduction to Cu electromigration

Electromigration is a major reliability concern in today’s integrated circuits due to the aggressive scaling of interconnect dimensions and the ever-increasing current densities at operation. In addition, the recent introduction of new materials and processing schemes lead to even more challenges in guaranteeing interconnect robustness against electromigration failure. In this article, we review basic electromigration physics in which the main differences between Al- and Cu-based interconnects relevant to electromigration are covered. We also discuss recent process-related advances in electromigration reliability such as the use of alloys and metal caps. Next, the impact of low-k inter-level dielectrics (ILD) on electromigration performance is addressed. Finally, the methodology of electromigration lifetime extrapolation, including reliability assessments of more complex interconnect geometries, is covered.     

A comprehensive model of PMOS NBTI degradation

Negative bias temperature instability has become an important reliability concern for ultra-scaled Silicon IC technology with significant implications for both analog and digital circuit design. In this paper, we construct a comprehensive model for NBTI phenomena within the framework of the standard reaction–diffusion model. We demonstrate how to solve the reaction–diffusion equations in a way that emphasizes the physical aspects of the degradation process and allows easy generalization of the existing work. We also augment this basic reaction–diffusion model by including the temperature and field-dependence of the NBTI phenomena so that reliability projections can be made under arbitrary circuit operating conditions.     

Dynamically inserting, operating, and eliminating thermal sensors of FPGA-based systems

In this paper, a new thermal monitoring strategy suitable for field programmable logic array (FPGA)-based systems is developed. The main idea is that a fully digital temperature transducer can be dynamically inserted, operated, and eliminated from the circuit under test using run-time reconfiguration. A ring-oscillator together with its auxiliary blocks (basically counting and control stages) is first placed in the design. After the actual temperature of the die is captured, the value is read back via the FPGA configuration port. Then, the sensor is eliminated from the chip in order to release programmable resources and avoid self-heating. All the hardware of the sensor is written in Java, using the JBits API provided by the chip manufacturer. The main advantage of the technique is that the sensor is completely stand-alone, no I/O pads are required, and no permanent use of any FPGA element is done. Additionally, the sensor is small enough to arrange an array of them along the chip. Thus, FPGAs became a new tool for researchers interested in the thermal aspects of integrated circuits.     

Yield optimization in wafer scale circuits with hierarchical redundancies

For wafer scale integration, the concept of redundancy is important to yield enhancement and circuit repairability. In designing today's complex VLSI circuits, structured hierarchical design methodology in which a chip is partitioned into different levels of building blocks is generally preferred. The question naturally arises: Can hierarchy of redundancies be used to advantage? To maximize the circuit yield, we are therefore concerned with the size of the block at each level and the distribution of redundancies among blocks. This paper analyses the relationship between yield and the redundancy distribution for a two-level chip architecture with a given over-all redundancy overhead factor.     

基于ADE7878的多路电量检测系统设计

为了解决工控领域多路交流电参数检测,需要独立进行单路测量电路设计的问题,给出了一种基于ADE7878芯片和嵌入式技术设计的多路电参数采集系统的硬件电路和程序流程。系统采用LPC2132作为主控芯片,适时控制4052多路开关,切换各路信号,通过I2C通信接口,读取ADE7878电能芯片采集的电量参数,同时通过RS485通信接口,上传电参数。实验结果表明,该采集系统最多可采集4路三相电的电压,电流,功率,功率因数,电能均能实现1%的计量精度,具有应用灵活,外围电路简单,可靠性高,成本低的特点。本电路设计亦可为相关产品的测试系统研发提供参考。     

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Reducing average and peak temperatures of VLSI CMOS circuits by means of evolutionary algorithm applied to high level synthesis

In this paper an adaptive evolutionary algorithm (AEA) for high-level synthesis, resulting in reduction of the power dissipation in CMOS circuits is presented. It enables us to design contemporary electronic circuits/systems with minimisation of the peak and average power consumption, which leads to reduction of the peak and average temperature of the designed chip. Therefore, the reliability of the integrated circuit (IC) can be improved. The results of experiments carried out for the chosen benchmark circuits show that the achieved reduction of power consumption varies from 4 to 52%.     

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.     

基于FPGA的集成电路测试系统设计

随着电路设计技术的不断发展,集成电路的测试对保证电路可靠性的作用日益增加。集成电路的测试不仅对确保电路的可靠性有重要作用,而且可以降低电路与系统的制造成本。本文是基于集成电路的逻辑功能测试理论,通过测试集成电路的逻辑功能是否正常来判断电路功能是否正常。实验结果表明,该系统测试便捷,准确,对于芯片的生产商和使用者都具有较重要的意义。     

基于C8051F120的以太网数据采集的技术研究

随着嵌入式的发展,基于WEB的应用开发已经进入了工业控制领域.本系统实现在CYGNAL公司8位单片机嵌入裁减的TCP/IP协议,完成了单片机的Internet接入和温度的数据采集,给出了嵌入式通信的硬件电路设计和软件实现.     

CMOS集成电路的自热效应和均匀温度分布的电热耦合模拟

集成电路实际是由相互耦合的电学子系统和热学子系统共同组成。本文基于具体的封装结构提出集成电路的热学分析模型,分析了温度对集成电路性能和功耗的影响。并且针对均匀温度分布的集成电路,采用解耦法实现了电热耦合模拟软件ＥＴｓｉｍ。     

An Integrated Approach to Thermal Management in High-Level Synthesis

Thermal effects are becoming an important factor in the design of integrated circuits due to the adverse impact of temperature on performance, reliability, leakage, and chip packaging costs. Making all phases of the design flow aware of this physical phenomenon helps in reaching faster design closure. In this paper, we present an integrated approach to thermal management in architectural synthesis. Our synthesis flow combines temperature-aware scheduling and binding based on feedback from thermal simulation. We show that our flow is effective in preventing hotspot formation and creating an even thermal profile of the resources. Our integrated thermal management technique on average reduces the peak temperature of the resources by 7.34 degC when compared to a thermal unaware flow without increasing the number of resources across our set of benchmarks     

基于迟滞比较器的过热保护电路设计

为了防止芯片过热,提高芯片可靠性和稳定性,采用0.5μm CMOS工艺,设计了一种具有迟滞比较器的过热保护电路。由于采用了折叠式运放,使得比较器输入范围更大,灵敏度和迟滞性能更好。利用Cadence Spectre仿真工具对电路进行了仿真,结果表明电源电压为4.5～7 V时,过温保护阈值变化量极小,表现出输出信号对电源的良好抑制。当温度超过130℃时,输出信号翻转,芯片停止工作;温度降低至90℃时,芯片恢复工作。此电路可以通过调整特定管子的尺寸而控制两个阈值电压的大小,从而避免热振荡的发生。