A finite weakest-link model of lifetime distribution of high-k gate dielectrics under unipolar AC voltage stress

This paper presents a new probability distribution function for the breakdown lifetime of high-k gate dielectrics under unipolar AC voltage stress. This function is derived from a finite weakest-link model, where the gate oxide layer is considered to consist of many potential breakdown cells. Each potential breakdown cell is modeled as a series coupling of several subcells, which is analogous to the fiber-bundle model for the strength statistics of structures. The present model indicates that the type of lifetime distribution varies with the gate area and the dependence of the mean lifetime on the gate area deviates from the classical Weibull scaling law. It is shown that the model agrees well with the observed lifetime histograms of HfO₂ based gate dielectrics under unipolar AC voltage stress.     

Threshold voltage instability characteristics of HfO2 dielectrics n-MOSFETs

In this paper, the threshold voltage instability characteristics of HfO₂ high-k dielectric are discussed. The results from various stress bias conditions including DC and AC with variations of frequency, duty cycle, and polarity provide additional insights into the intrinsic behavior and the trapping dynamics of high-k materials. A reduced threshold voltage shift was observed at higher frequency and lower duty cycle under AC positive unipolar stress compared to DC stress. Similarly, the degradation of maximum transconductance was also reduced with AC stress. However, subthreshold swing changes were found to be negligible and fairly independent of stress frequencies and duty cycles under AC positive unipolar stress.When different polarity of stress, such as positive, negative, and bipolar stress was applied, it was observed that frequency and duty cycle dependencies were still valid in all three conditions. In contrast to positive stress, negative stress showed a decrease in the threshold voltage shift. Bipolar stress resulted in the highest threshold voltage instability, but the degradation in transconductance and subthreshold swing was actually smaller than those in negative unipolar stress. The bulk trap of HfO₂ dielectric, which is proportional to its physical thickness, is believed to be the primary factor for threshold voltage shift. AC unipolar operation would allow a higher 10-year lifetime operating voltage than the DC condition. In addition to experimental results, a plausible mechanism has been proposed.     

New electronic effects in double injection diodes with one deep level

Double injection diodes made of high resistivity semiconductors compensated with deep levels show a negative differential resistance region in the stationary I - V characteristic. At lower temperatures the injection level of free carriers can be altered within the prebreakdown region without changing the space charge situation. Therefore is valid for several orders of magnitude of the current. Furthermore, the switching of the diode from the “off state” (prebreakdown region) to the “on-state” (high injection or semiconductor regime) can be delayed by applying a corresponding voltage V >V_BD, the breakdown voltage. An exponential dependence of the delay time t_D on the applied voltage is found. The lower limit of t_D is determined by the free carrier lifetime, an upper limit does practically not exist if the temperature is low enough.     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

Dielectric reliability of stacked Al2O3–HfO2 MIS capacitors with cylinder type for improving DRAM data retention characteristics

Dielectric reliability in Al₂O₃(2–3.1nm)–HfO₂(3nm) stack capacitor with Metal–Insulator–Si(MIS) structure is investigated in this paper. We propose an optimized capacitor process through the Time–Dependent Dielectric Breakdown (TDDB) data under various process conditions. Furthermore, due to asymmetric current at both negative and positive voltage stress polarities, we show different lifetime extrapolation by a fluence–driven model. As a result, the maximum allowed operating voltage is projected to be 1.7V (failure rate 10ppm during 10year @ 85°C) for Data “0” retention lifetime.     

Electrical reliability aspects of HfO2 high-k gate dielectrics with TaN metal gate electrodes under constant voltage stress

The dielectric breakdown property of ultrathin 2.5 and 5.0 nm hafnium oxide (HfO₂) gate dielectric layers with metal nitride (TaN) gate electrodes for metal oxide semiconductor (MOS) structure has been investigated. Reliability studies were performed with constant voltage stressing to verify the processing condition effects (film thicknesses and post metal annealing temperatures) on times to breakdown. The leakage current characteristics are improved with post metal annealing temperatures (PMA) for both 2.5 and 5.0 nm HfO₂ physical thicknesses. However, it is more prominent (2 orders of magnitudes) for 2.5 nm HfO₂ film thickness. The values of oxide-trapped charge density and interface-state density are also improved for 2.5 nm HfO₂ film. The different stages of charge-trapping behaviors, i.e., stress-induced leakage current, soft and hard breakdown mechanisms have been detected. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate current is observed, followed by the occurrence of several fluctuations. The amplitude of the fluctuations is much larger in the 5.0 nm HfO₂ gate dielectric layer compared to the 2.5 nm HfO₂ layer. After the occurrence of such fluctuations, the current–voltage characteristics exhibited an increased in gate current compared to the fresh (unstressed) devices.     

Time-dependent dielectric breakdown (TDDB) distribution in n-MOSFET with HfSiON gate dielectrics under DC and AC stressing

This paper discusses time-dependent dielectric breakdown (TDDB) in n-FETs with HfSiON gate stacks under various stress conditions. It was found that the slope of Weibull distribution of T_bd, Weibull β, changes with stress conditions, namely, DC stress, unipolar AC stress and bipolar AC stresses. On the other hand, the time evolution component of stress-induced leakage current (SILC) was not changed by these stresses. These experimental results indicate that the modulation of electron trapping/de-trapping and hole trapping/de-trapping by stress condition changes the defect size in high-k gate dielectrics. Therefore, the control of injected carrier and the characteristics of trapping can provide the steep Weibull distribution of T_bd, leading to long-term reliability in scaled CMOS devices with high-k gate stacks.     

Breakdown and reliability of p-MOS devices with stacked RPECVD oxide/nitride gate dielectric under constant voltage stress

In this work, the effects of voltage and temperature on the TDDB characteristics of 2.0 nm stacked oxide/nitride (O/N) dielectric, prepared by remote plasma enhanced CVD (RPECVD), has been investigated. The breakdown characteristics and time-to-breakdown (t_BD) are recorded from p⁺-poly/n-Si capacitors under constant voltage stress (CVS) at different temperatures. The t_BD cumulative distributions exhibit a single Weibull slope β of 1.9 for different applied voltages. The charge-to-breakdown (Q_BD) is integrated from the gate current as a function of stress times, and can be used to extract the defect generation rate. The activation energy of 0.39 eV is determined from the Arrhenius law, and the average temperature acceleration factor is about 45 between 25 and 125 °C for a constant gate voltage. The extrapolation of the TDDB lifetime with low percentile failure rate of 0.01% provides a 10-year projection for a total gate area of 0.1 cm² on a chip at 125 °C with the Poisson area-scaling law and a constant voltage acceleration factor of 14.83 V⁻¹. It is projected that the maximum safe operating voltage is 1.9 V for 2.07 nm O/N gate dielectric.     

Influences of bottom electrode TaN on electrical characteristics for metal–HfO2–metal capacitors

For TaN–HfO₂–TaN_x capacitors, the effects of bottom electrode TaN_x with different nitrogen contents on electrical characteristics are exhibited. An obvious oxygen deficiency can be found in HfO₂ film by AES analysis for the sample with bottom electrode TaN_x sputtered at a N₂/(N₂ + Ar) flow ratio of 10%. The bottom electrode TaN_x films with different nitrogen contents apparently affect HfO₂/TaN_x interfacial property and electrical characteristic of follow-up deposited HfO₂ film. Experimental results reveal that the more defective TaN_x structure can induce more oxygen vacancies in subsequently deposited HfO₂ film and result in a higher leakage current density and a worse breakdown electric field. Two factors affect these electrical characteristics including interfacial stress and oxygen vacancy. It indicates that interfacial stress due to various stochiometric TaN_x structure dominates the voltage linearity property of capacitance, but more leak paths and local field breakdown defects can be induced by interfacial stress and oxygen vacancy. Better electrical characteristics can be attained for the sample with bottom electrode TaN_x sputtered at a N₂/(N₂ + Ar) flow ratio of 20%.     

Time-dependent dielectric breakdown of SiO2 films in a wide electric field range

We have performed time dependent dielectric breakdown measurement of SiO₂ films in the electric field (E_OX) range 7–13.5 MV/cm and evaluated the electric field dependence of intrinsic lifetime, using both area and temperature dependences of oxide lifetime. We have evaluated the electric field dependence of time to breakdown (t_BD) below 125°C, because the activation energy of intrinsic lifetime changes at 125°C t_BD of 7.1 and 9.6 nm oxides is not proportional to exp(E_OX) but proportional to exp(1/E_OX). This suggests that the breakdown mechanism of 9.6 and 7.1 nm oxides is the same and adheres to the anode hole injection model. However, the breakdown mechanism of 4.0 nm oxides is not the same as that of 7.1 and 9.6 nm oxides. The slope of log(t_BD) versus 1/E_OX plot in 4.0 nm oxide increases with decreasing oxide fields. The intrinsic lifetime in the positive gate bias decreases with increasing oxide thicknesses in the range of electric fields employed in the present experiment.     

Electrical characterization of HfO2 films obtained by UV assisted injection MOCVD

HfO₂ films were deposited at low temperature (400 °C) by UV assisted injection metal-organic chemical vapor deposition (UVI-MOCVD). A three-step process was used for this study, consisting of (A) Pre-deposition anneal for nitridation; (B) Deposition step; (C) Post-deposition annealing in oxygen. Special attention was paid to the effect of UV exposure during these steps. Films were characterized by physical, optical and electrical techniques. Thickness was determined by different methods (X-ray Reflectrometry (XRR), spectroscopic ellipsometry and transmission electron microscopy) and a good agreement was found for all samples. The HfO₂ permittivity, equivalent oxide thickness (E_OT), flat-band voltage (V_fb) and total charge (Q_t) were extracted from the CV response at high frequency taking into account the HfO₂ and SiO₂ thicknesses obtained by XRR. The calculated permittivity values were in the range 7–13, i.e. lower than theoretical values for the monoclinic phase. Explanations are suggested in the context of the other characterizations. JE_eff characteristics were constructed taking into account the E_OT values (E_eff = V/E_OT). Effective breakdown fields range between 8.7 and 16.9 MV/cm. No dependence of E_eff with UV exposure was found.     

Effects of the electrical stress on the conduction characteristics of metal gate/MgO/InP stacks

The degradation dynamics and post-breakdown current–voltage (I–V) characteristics of magnesium oxide (MgO) layers grown on n and p-type indium phosphide (InP) substrates subjected to electrical stress were investigated. We show that the current–time (I–t) characteristics during degradation can be described by a power-law model I(t) = I₀t^−α, where I₀ and α are constants. It is reported that the leakage current associated with the soft breakdown (SBD) failure mode follows the typical voltage dependence I = aV^b, where a and b are constants, for both injection polarities but in a wider voltage range compared with the SiO₂/Si system. It is also shown that the hard breakdown (HBD) current is remarkably high, involving large ON–OFF fluctuations that resemble the phenomenon of resistive switching previously observed in a wide variety of metal oxides.     

Electrical characterisation and reliability of HfO2 and Al2O3–HfO2 MIM capacitors

Current leakage and breakdown of MIM capacitors using HfO₂ and Al₂O₃–HfO₂ stacked layers were studied. Conduction in devices based upon HfO₂ layers thinner than 8 nm is probably dominated by tunnelling. Al₂O₃–HfO₂ stacked layers provide a limited benefit only in term of breakdown field. Constant-voltage wear-out of samples using insulating layer thicker than 6 nm is dominated by a very fast increase of the leakage current. A two step mechanism involving the generation of a conduction path followed by a destructive thermal effect is proposed to explain breakdown mechanism.     

Oxide reliability: influence of interface roughness, structure layout, and depletion layer formation

The charge to breakdown Q_bd and the breakdown voltage V_bd distributions obtained on 7.5 and 12 nm thick gate oxides (GOX) using two different wafer level reliability current ramp algorithms are discussed in terms of the GOX interface roughness and the depletion effects during the stress. The observed influence of the interface roughness on the GOX properties seems to be very sensitive to the gate polarity during the stress or the injection direction of electrons. Especially the roughness of the interface through which electrons are injected into the gate oxide influences the oxide reliability. The effect of the interface roughness turned out to depend strongly on the test acceleration level. A possibility of masking of the roughness (reduction of the “effective roughness”) of the GOX/Si interface as a result of strong depletion at higher accelerations is discussed.     

Dielectric breakdown characteristics and interface trapping of hafnium oxide films

The reliability and integrity of HfO₂ prepared by direct sputtering of hafnium were studied. By monitoring the current-voltage and current-stressing duration characteristics, we found a significant charge trapping effect in thin film with very short stressing time (<30 s) but the stress-induced trap generation is insignificant. The breakdown characteristics of hafnium gate oxide were also investigated in detail. We found that several soft breakdowns take place before a hard breakdown. Area and stress-voltage effects of the time-dependent dielectric breakdown were observed. Results suggest that the soft and hard breakdowns should have different precursor defects. A two-layer breakdown model of is proposed to explain these observations.     

Breakdown characteristics of nFETs in inversion with metal/HfO2 gate stacks

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO₂ high-κ gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin high-κ layers (?3.3 nm), breakdown (BD) voltage during RVS is controlled by the critical electric field in the interfacial layer (IL), while in the case of thicker high-κ stacks, BD voltage is defined by the critical field in the high-κ layer. Under low gate bias CVS, one can observe different regimes of the gate leakage time evolution starting with the gate leakage current reduction due to electron trapping in the bulk of the dielectric to soft BD and eventually hard BD. The duration of each regime, however, depends on the IL and high-κ layer thicknesses. The observed strong correlation between the stress-induced leakage current (SILC) and frequency-dependent charge pumping (CP) measurements for the gate stacks with various high-κ thicknesses indicates that the degradation of the IL triggers the breakdown of the entire gate stack. Weibull plots of time-to-breakdown (T_BD) suggest that the quality of the IL strongly affects the TDDB characteristics of the Hf-based high-κ gate stacks.     

Time-dependent-dielectric-breakdown characteristics of Hf-doped Ta2O5/SiO2 stack

The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta₂O₅ films (8 nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta₂O₅ were compared. The doped Ta₂O₅ exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10 years lifetime at room temperature is −2.4 V. The presence of Hf into the matrix of Ta₂O₅ modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.     

Reliability studies of barrier layers for Cu/PAE low-k interconnects

Electromigration and electrical breakdown are two of the most important concerns in the reliability of modern electronic devices. The electromigration lifetimes and electrical breakdown field (E_BD) in single damascene copper lines/porous polyarylene ether (PAE) dielectric with different diffusion barrier materials (i.e., amorphous-SiC:H and TaN/Ta) were studied. The results showed a “wafer edge effect” in both groups of samples. The electromigration lifetime of samples taken from the center of the wafer is five to nine times longer of those taken from the wafer edge in the accelerated test. The samples from wafer edge showed a bi-modal failure characteristic. It was also found that electromigration resistance of the structure with new diffusion barrier a-SiC:H/Ta was comparable to that with the conventional TaN/Ta. On the other hand, the electrical testing showed that E_BD of the a-SiC:H/Ta structure is about twice of that with TaN/Ta barrier, indicating a significant improvement of the electrical performance.     

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO2 and HfO2/SiO2 gate dielectric stacks

We compare charge carrier generation/trapping related degradation in control oxide (SiO₂) and HfO₂/SiO₂ stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiOSi bonds in either of the devices. We demonstrate that compared to SiO₂ devices, HfO₂ devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO₂ devices at a given operating voltage.     

Influence of fluorine contamination on reliability of thin gate oxides

We analyze diffusion and segregation kinetics of fluorine atoms in poly-Si / SiO₂ / Si structures with gate oxides of 5 nm by means of secondary ion mass spectroscopy. Well defined doses of fluorine were introduced by ion implantation. Our results indicate fluorine segregation at interfaces to the gate oxide. This segregation is diffusion limited with an effective activation energy of 1.4 eV. The accumulation of fluorine influences the intrinsic reliability of thin oxides. The breakdown behavior was studied using constant voltage, constant current, and stepwise increasing constant current stress, respectively. Weibull plots before and after the heat treatments were analyzed. At low fluorine concentrations up to doses of 5 × 10¹⁵ cm⁻² fluorine segregation is beneficial, improving, for example the tails of the Weibull plots and slightly increasing the breakdown voltage. For fluorine doses higher than 1 × 10¹⁶ cm⁻², detrimental consequences were found, degrading the charge to breakdown values by about a factor of 5 after long - term thermal treatments.