Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the g_m/I_D characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the g_m/I_D characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.     

Bulk and surface degradation mode in 0.35μm technology gg-nMOS ESD protection devices

We study failure mechanisms in 0.35μm process grounded-gate nMOS electrostatic discharge (ESD) protection devices stressed by high current - ESD like - pulses. Stress evolution of leakage current and low frequency noise is correlated with the position of the ESD damage analyzed using optical beam induced current (OB1C) technique. While a kink-free-like IV characteristics and low noise magnitude are typical for a bulk damage at the drain-contact region, a kink-like IV shape and large random telegraph signal (RTS) noise accompanies surface damage under the gate oxide. The role of hot-carriers in the degradation of the Si/Si0₂ interface and gate oxide, and leakage current mechanism are discussed.     

Hot-carrier reliability of 20V MOS transistors in 0.13 μm CMOS technology

This paper presents results of reliability investigation of 20 V N-Drift MOS transistor in 0.13 μm CMOS technology. Due to high performances required for CMOS applications, adding high voltage devices becomes a big challenge to guarantee the reliability criteria. In this context, new reliability approaches are needed. Safe Operating Area are defined for switch, V_ds limited and V_gs limited applications in order to improve circuit designs. For V_ds limited applications, deep doping dose effects in drift area are investigated in correlation to lifetime evaluations based on device parameter shifts under hot carrier stressing. To further determine the amount and locations of hot carriers injections, accurate 2D technological and electrical simulations are performed and permit to select the best compromise between performance and reliability for N-Drift MOS transistor.     

A 1.7 Gbps DLL‐Based Clock Data Recovery for a Serial Display Interface in 0.35‐μm CMOS

This paper presents a delay‐locked‐loop–based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high‐speed serial display interface. The nB(n+2)B data is formatted by inserting a ‘01’ clock information pattern in every piece of N‐bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7‐Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high‐performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3‐V power supply using a 0.35‐μm CMOS process and the measured peak‐to‐peak jitter of the recovered clock is 44 ps.     

Scaling of poly-encapsulated LOCOS for 0.35 μm CMOS technology

We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 μm CMOS technology without detrimental effects on gate oxide and shallow source/drain junction integrity. As-grown bird's beak punchthrough is shown to fundamentally limit the scalability of LOCOS-based schemes for narrow nitride features. A quantitative comparison of bird's beak punchthrough is made between LOCOS, Poly-Buffer LOCOS (PBL), and PELOX. The PELOX scalability is emphasized by evaluating the impact of the polysilicon-sealed cavity length for narrow nitride features. We present the realization of a 1 μm active/isolation pitch fully meeting the geometry and off-leakage requirements of 0.35 μm CMOS technologies (VDS⩽5 V). This field-implant-free isolation module avoids unnecessary process complexity by successfully integrating scaled PELOX with the split well-drive-in scheme. A highlight of this new approach is that the NMOSFET characteristics are largely width-independent down to 0.3 μm dimensions     

Design and optimization of high voltage LDMOS transistors on 0.18 μm SOI CMOS technology

In this paper, we have studied the effect of systematic downscaling of MOS channel length of the performance of the hybrid GaN MOS-HEMT with numerical simulations. The improvement in on-state conduction, together with concomitant short channel effects, including drain induced barrier lowering (DIBL) is quantitatively evaluated. A specific on-resistance of 2.1 mΩ cm² has been projected for a MOS channel length of 0.38 μm. We also have assessed the impact of high-k gate dielectrics, such as Al₂O₃. In addition, we have found that adding a thin GaN cap layer on top of AlGaN barrier can help reducing short channel effects.     

TLP analysis of 0.125 μm CMOS ESD input protection circuit

In this investigation, TLP ESD analysis shows that if a large input resistor is used in combination with a secondary ggNMOS clamp in the input protection circuitry, then the trigger voltage, V_t1, of the ggNMOS clamp is not a constant. The value is influenced by the size and properties of the input resistor, by current injection problems due to parallel resistive networks formed between the primary and secondary ESD circuits, by reverse bias diode leakage currents effects, and by source elevation effects due to voltage rises along the ESD ground bus.     

A 0.18 μm CMOS linear-in-dB AGC post-amplifier for optical communications

This paper presents a fully integrated 10GBase-LX4 Ethernet receiver front-end automatic gain control amplifier realized in a 0.18 μm CMOS process. Based on a very compact and reliable inductorless design, the proposed differential post-amplifier, comprises three main digitally programmable gain stages, a DC offset cancellation network and an automatic gain feedback control loop. Experimental results demonstrate a −3 dB cut-off frequency above 2.3 GHz over a −3 to 33 dB linear-in-dB controlled gain range with a sensitivity of 2.0 mV_p-p with a BER of 10⁻¹² at 2.5 Gb/s. For the aforementioned standard, 3.125 Gb/s, an input dynamic range above 50 dB is achieved, from 2.5 mV_p-p to 800 mV_p-p, indicating a BER of 10⁻¹². The chip core area is 0.3 × 0.3 mm² and it consumes 58 mW with a single supply voltage of 1.8 V.     

Practical compact modeling approaches and options for sub-0.1 μm CMOS technologies

This paper attempts to provide a general overview and guideline to develop a practical model for CMOS devices in the sub-0.1μm generations. It starts by giving an overview of the different modeling options including the charge-based approach, the surface potential based approach, and the conductance-based approach. Their relative advantages and weaknesses will be discussed. The evolution of the BSIM models from its first generation to the most recent release will be used as an example for the development of a practical device model. It will be followed by a discussion on how the accelerated technology development may impact the traditional modeling methodologies. A new paradigm to incorporate modern software engineering methodology to shorten model development cycle will be presented.     

W‐Band MMIC chipset in 0.1‐μm mHEMT technology

We developed a 0.1‐μm metamorphic high electron mobility transistor and fabricated a W‐band monolithic microwave integrated circuit chipset with our in‐house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz–108 GHz band and achieved excellent spurious suppression. A low‐noise amplifier (LNA) with a four‐stage single‐ended architecture using a common‐source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W‐band image‐rejection mixer (IRM) with an external off‐chip coupler was also designed. The IRM provided a conversion gain of 13 dB–17 dB for RF frequencies of 80 GHz–110 GHz and image‐rejection ratios of 17 dB–19 dB for RF frequencies of 93 GHz–100 GHz.     

Reliability aspects of thermal micro-structures implemented on industrial 0.8 μm CMOS chips

This paper discusses the reliability characterization of thermal micro-structures implemented on industrial 0.8 μm CMOS chips. Various degradation and failure mechanisms are identified and evaluated under high temperature operation. At high temperatures the mechanisms are many and varied, and co-incidental thermally-induced mechanical defects are found in both the poly-Si heater and the poly-Si temperature sensor, along with temperature- and current-enhanced interlayer diffusion degradation of the heater contacts. Local reduction in the device thermal capacity by using silicon micro-machining can be expected to hold the promise of a number of significant advantages, especially for limiting current stressing of the contact regions. The results can be used to optimize the design of thermally based micro-sensors on CMOS chips, such as CMOS compatible chemoresistive gas sensors.     

Investigation on seal-ring rules for IC product reliability in 0.25-μm CMOS technology

The distance between active region and the seal-ring location has been investigated in a 0.25-μm CMOS process. From the experimental results, this distance can be shrunk to only 5 μm without increasing leakage current and decreasing ESD robustness of the ESD protection devices after reliability tests of High-Accelerated Stress Test (HAST) and Temperature Cycling Test (TCT).     

A family of low-power truly modular programmable dividers instandard 0.35-μm CMOS technology

A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 μm bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider     

Development of substrate-pumped nMOS protection for a 0.13 μm technology

A methodology is presented for improved process and circuit development of substrate-pumped nMOS protection. ESD process development is accelerated by applying factor analysis to completed non-ESD experiments. Factor analysis is complemented by a straightforward diagnosis of nMOS snapback. This approach enabled verification of two process solutions, including a novel method, in one fab cycle-time. HBM data that shows the substrate-pumped nMOS can provide dramatically higher protection than estimated from conventional I_t2 measurements. This motivates improved ESD circuit development. The nMOS clamp transistor is characterized as an actively biased LNPN, which is how it is used in a substrate-pumped protection circuit. A systematic approach to circuit development is described that is based upon empirical characterization of well-defined circuit components under conditions approximating ESD.     

Open contact analysis of single bit failure in 0.18 μm technology

Single bit failure is the most common failure mode in static random access memory. Although a failing cell can be easily localized with bitmap data, the exact defect location within the failing cell cannot be found immediately, especially when a defect is related to contact. In this paper, a technique of contact-level passive voltage contrast has been proposed to detect such defects for a single bit failure. After an open contact was identified, subsequent transmission electron microscope analysis was performed and it was found that the root cause for the open contact was poly residue.     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

On-chip matched 5.2 and 5.8 GHz differential LNAs fabricated using0.35 μm CMOS technology

The authors have designed experimental 5.2 and 5.8 GHz low-noise amplifiers (LNAs) using 0.35 μm CMOS technology. The ICs feature on-chip matching to 50 Ω, differential operation, and open drain output buffers. A return loss of better than -15 dB was achieved for both amplifiers. LC parallel resonant loads were used to form the gain peak. The LNAs had a measured noise figure of 4 to 5 dB, at VSS=3.3 V     

Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-/spl mu/m CMOS technology

The dual-modulus prescaler is a critical block in CMOS systems like high-speed frequency synthesizers. However, the design of high-moduli, high-speed, and low-power dual-modulus prescalers remains a challenge. To face the challenge, this paper introduces the idea of using transmission gates and pseudo-PMOS logic to realize the dual-modulus prescaler. The topology of the prescaler proposed is different from prior designs primarily in two ways: 1) it uses transmission gates in the critical path and 2) the D flip-flops (DFFs) used in the synchronous counter comprise pseudo-PMOS inverters and ratioed latches. A pseudo-PMOS logic-based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35-/spl mu/m CMOS technology. It consumes 4.8 mW from a 3-V supply. The measured phase noise is -143.4 dBc/Hz at 600 kHz. The silicon area required is only 0.06 mm/sup 2/. There are no flip flops or logic gates in the critical path. This topology is suitable for high-speed and high-moduli prescaler designs. It reduces: 1) design complexity; 2) power consumption; and 3) input loading. Measurement results are provided. An improvement in the figure of merit is shown.     

Low frequency noise in 0.12 μm partially and fully depleted SOI technology

Low frequency noise characterization of 0.12 μm silicon-on-insulator (SOI) CMOS technology is for the first time performed for partially and fully depleted N-MOSFETs. Static performances of the experimental devices are first presented, then we address the drain current fluctuations in both linear and saturation regimes. Taking into consideration the usually admitted 1/f noise models in MOS devices and their applicability in our case, we point out an enhancement of the extracted trap densities for both architectures compared to previously obtained results in 0.25 μm SOI CMOS technology. As regards drain current spectral densities in saturation mode, we notice some peculiarities occurring for the Kink-related excess noise.     

K-band low-noise amplifiers using 0.18 /spl mu/m CMOS technology

Two K-Band low-noise amplifiers (LNAs) are designed and implemented in a standard 0.18 /spl mu/m CMOS technology. The 24 GHz LNA has demonstrated a 12.86 dB gain and a 5.6 dB noise figure (NF) at 23.5 GHz. The 26 GHz LNA achieves an 8.9 dB gain at the peak gain frequency of 25.7 GHz and a 6.93 dB NF at 25 GHz. The input referred third-order intercept point (IIP3) is >+2 dBm for both LNAs with a current consumption of 30 mA from a 1.8 V power supply. To our knowledge, the LNAs show the highest operation frequencies ever reported for LNAs in a standard CMOS process.