A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchicalsquare-shaped memory block and distributed bank architecture

This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 μm² cell and 581.8 mm² small die area are achieved using 0.15-μm CMOS technology. The ×61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described     

DRAM reliability

Dynamic random access memory (DRAM) reliability is investigated for future DRAMs where small geometrical devices are used together with new materials and novel process technologies. Among the several items of DRAM reliability, the most important aspect to consider for DRAM reliability is infant mortality which is caused by process-induced defects including random defects. Since the process-induced defects are strongly dependent on process technology, it is inevitable to minimize process-induced defects by developing new process technology. However, whenever new process technology is introduced, new screening techniques or methods are necessary for suppressing infant mortality. The degradation of pMOSFET due to buried-channel pMOSFET during burn-in stress and soft error rate due to α-particle and cosmic ray irradiation become concerns as device dimension shrinks. However, it cannot be limitations of DRAM reliability because pMOSFET degradation due to hot electron induced puchthrough can be suppressed by new layout of pMOSFET, and the soft error events can be overcome by soft error resistant device structure and proper material choices. From these considerations, it can be expected that the advances of DRAM technology generation not only improve the device performance but also enhance the reliability.     

Performance characteristics of SOI DRAM for low-power application

Process integration of cell capacitors that can circumvent the usual difficulties of large topographic height difference and high-temperature process are presented. A 16 Mbit silicon-on-insulator (SOI) DRAM with a 0.3 μm design rule is successfully fabricated and analyzed for processing integrity and circuit performance based on process integration of the cell capacitor using the pattern-bonded SOI (PBSOI) technology. Measurements for the strobe access time (tRAC) acid the operation current (I_ccl) show significant improvement (over 25%) for the SOI DRAM compared to those for the 16 Mbit bulk counterpart with the same circuit and layout. On the transistor side, ultra-low-voltage transistor technology using the body bias control schemes is also implemented and investigated. Devices with small leakage current and almost ideal subthreshold swing are obtained. The results give us guidance for transistor and process schematics for low-voltage DRAM application     

Impact of preanneal process on threshold voltage of MOS transistors for trench DRAM

As the first step of DRAM manufacture, preanneal process plays an important role in determining the threshold voltage variation. It is found that the higher trans-1,2-dichloroethene flow in pad oxide growth and the higher nitrogen flow in high-temperature annealing step would respectively engender a lower boron segregation coefficient and higher nitridation of the oxide, both modify the boron distribution in the substrate and consequently the behavior of the threshold voltage. As the feature size of DRAM devices enter nanometer regime, besides gate oxidation, ion implantation and related thermal processes, the impact of preanneal process condition should be prudentially taken into consideration for rigorous control of the threshold voltage in the advanced DRAM production.     

3D集成的发展现状与趋势

三维集成技术的发展是技术与理念的革新过程,本文根据集成封装技术的的发展历程,提出三维集成的发展特点,阐述理念的突破如何引导技术发展,以此为主线,可以更有逻辑性的了解三维集成的发展历史与趋势.封装从器件级向系统级的发展促使了多种系统级封装概念的出现;垂直堆叠方式推动互连长度不断降低;与晶圆级封装的结合可以大幅度降低成本;从同质向异质的转变则集成了多种学科、材料与技术,是实现复杂的系统的基础.     

A review:aluminum nitride MEMS contour-mode resonator

Over the past several decades, the technology of micro-electromechanical system (MEMS) has advanced. A clear need of miniaturization and integration of electronics components has had new solutions for the next generation of wireless communications. The aluminum nitride (AlN) MEMS contour-mode resonator (CMR) has emerged and become promising and competitive due to the advantages of the small size, high quality factor and frequency, low resistance, compatibility with integrated circuit (IC) technology, and the ability of integrating multi-frequency devices on a single chip. In this article, a comprehensive review of AlN MEMS CMR technology will be presented, including its basic working principle, main structures, fabrication processes, and methods of performance optimization. Among these, the deposition and etching process of the AlN film will be specially emphasized and recent advances in various performance optimization methods of the CMR will be given through specific examples which are mainly focused on temperature compensation and reducing anchor losses. This review will conclude with an assessment of the challenges and future trends of the CMR.     

Single-wafer integrated semiconductor device processing

The authors present an overview of various single-wafer fabrication techniques for integrated processing of microelectronic devices. Numerous processing modules, sensors, and associated fabrication processes have been developed for advanced semiconductor device manufacturing. The combination of single-wafer processing, cluster tools, sensors, and advanced factory control/computer-integrated manufacturing techniques provides a capability for flexible fast-cycle-time device manufacturing. Specific developments and results are described in the areas of dry/vapor-phase surface cleaning, epitaxy, plasma processing, rapid thermal processing, and in situ sensors. An integrated sub-half micrometer CMOS technology based on these single-wafer fabrication methods including rapid thermal processing is also described     

晶圆级多层堆叠技术

随着5G和人工智能等新型基础设施建设的不断推进,单纯通过缩小工艺尺寸、增加单芯片面积等方式带来的系统功能和性能提升已难以适应未来发展的需求。晶圆级多层堆叠技术作为能够突破单层芯片限制的先进集成技术成为实现系统性能、带宽和功耗等方面指标提升的重要备选方案之一。对目前已有的晶圆级多层堆叠技术及其封装过程进行了详细介绍;并对封装过程中的两项关键工艺,硅通孔工艺和晶圆键合与解键合工艺进行了分析;结合实际封装工艺对晶圆级多层堆叠过程中的可靠性管理进行了论述。在集成电路由二维展开至三维的发展过程中,晶圆级多层堆叠技术将起到至关重要的作用。     

系统级封装(SIP)技术及其应用前景

随着各种半导体新工艺与新材料水平的不断提高,先进的封装技术正在迅速地发展.本文综述了先进的系统级封装(SIP)技术的概念及其进展情况;并举例说明了它的应用情况,同时指出,SIP是IC产业链中知识、技术和方法相互交融渗透及综合应用的结晶.SIP封装集成能最大程度上优化系统性能、避免重复封装、缩短开发周期、降低成本和提高集成度,掌握这项新技术是进入主流封装领域之关键,有其广阔的发展前景.     

The state-of-the-art and future trends in DRAMs

The production of future generation DRAM devices critically requires R&D of process technologies for highly integrable and cost effective processes. Also, in order to support the ever-increasing requirements for high performance operation, the future DRAM products should be equipped with the capabilities of low voltage operation and high speed. This paper presents an overview of process technology for deep sub-micrometer devices such as a 256 Mbit DRAM based upon current research data and giga bit DRAMs.     

PELOX integrated PBL

Polysilicon buffered LOCOS (PBL) does not exhibit sufficient field oxide recess to support aggressive device scaling without the introduction of processes which are difficult to control. Recently, polysilicon encapsulated local oxidation (PELOX) has been proposed as an easily scaled isolation technique that exhibits LOCOS equivalent recess. The integration of PELOX into an existing PBL 1-Mb DRAM baseline process is described. PELOX-integrated PBL (PIPBL) is demonstrated to enhance final field oxide recess without increasing encroachment. The improved final field oxide recess is shown to provide increased process margin as evidenced by superior probe yield     

一种以过程为中心的基于工作流的信息系统开发与应用

文章从软件开发方法方面对信息系统中如何利用工作流技术来弥补传统信息系统对业务流程控制逻辑缺乏支持的缺陷，进行了深入研究.并提出了一种以过程为中心的信息系统概念，强调以组织的经营过程为主线来构筑信息系统，而不只是单纯从信息处理角度来考虑.对过程的支持主要利用工作流技术，它可以将过程与实现过程的功能和数据之间进行分离，从而提高信息系统对过程改变的灵活性。     

Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability.     

Fabrication of submicron junctions-proximity rapid thermaldiffusion of phosphorus, boron, and arsenic

Various techniques used in fabrication of deep submicron junctions are reviewed with respect to their advantages and disadvantages in silicon very large scale integration (VLSI) circuits technology. Proximity rapid thermal diffusion is then presented as an alternative process which results in very shallow junctions with high dopant concentrations at the surface. The feasibility of Si doping with B, P, and As for both planar and 3-D structures such as trench capacitors used in high density DRAM memories is shown based on sheet resistance measurements, secondary ion mass spectroscopy and scanning electron micrographs. Retardation effect of arsenic diffusion similar to the well known inhibition of silicon or SiO₂ deposition in chemical vapor deposition (CVD) processes is identified and discussed     

Modeling of Magnetic-Field-Assisted Assembly of Semiconductor Devices

The process of magnetic-field-assisted assembly for the integration of semiconductor devices is described. A simplified model that is relevant to both magnetically assisted statistical assembly and magnetic-field-assisted assembly is presented. This two-dimensional, periodic model, which is a development of earlier work by Fonstad and coworkers, is solved using Fourier series, and an expression is found for the magnetic force of attraction between a soft magnetic layer and an array of permanently magnetized strips. The results show an exponential decrease of force with distance and the dependence of the force on other parameters such as layer thickness and spacing.     

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

As CMOS processes advanced, the integration of radio-frequency (RF) integrated circuits was increasing. In order to protect the fully-integrated RF transceiver from electrostatic discharge (ESD) damage, the transmit/receive (T/R) switch of transceiver frond-end should be carefully designed to bypass the ESD current. This work presented a technique of embedded ESD protection device to enhance the ESD capability of T/R switch. The embedded ESD protection devices of diodes and silicon-controlled rectifier (SCR) are generated between the transistors in T/R switch without using additional ESD protection device. The design procedure of RF circuits without ESD protection device can be simplified. The test circuits of 2.4-GHz transceiver frond-end with T/R switch, PA, and LNA have been integrated and implemented in nanoscale CMOS process to test their performances during RF operations and ESD stresses. The test results confirm that the embedded ESD protection devices can provide sufficient ESD protection capability and it is free from degrading circuit performances.     

A process-independent, 800-MB/s, DRAM byte-wide interface featuringcommand interleaving and concurrent memory operation

An 800-MB/s/pin byte-wide interface DRAM is described that meets the bandwidth requirements for modern microprocessor systems. Clock recovery and I/O circuitry perform to specification across multiple DRAM manufacturers' processes. The clock-recovery circuitry is described in depth for areas that are sensitive to power-supply noise. I/O circuitry for preserving signal integrity in high-speed bussed systems is described. Design methodology that enables rapid simulation and verification of the design in each fabrication process is discussed. Logic that enables interleaved transactions with concurrent operation is detailed. Computer-aided-design tools for large aspect merged logic/memory are discussed. Last, measured results are summarized showing clock jitter, setup and hold timing, and period versus V_dd operation     

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor

This paper describes three circuit technologies that have been developed for high-speed large-bandwidth on-chip DRAM secondary caches. They include a redundancy-array advanced activation scheme, a bus-assignment-exchangeable selector scheme and an address-zero access refresh scheme. By using these circuit technologies and new small subarray structures, a row-address access time of 12 ns and a row-address cycle time of 16 ns were obtained. An experimental chip made up of an 8-Mbyte DRAM and a 64-bit microprocessor was developed using 0.25-μm merged logic and DRAM process technology     

TLM: a trench leakage monitor for a four megabit SPT DRAMtechnology

The authors discuss a single trench capacitor macro-array structure used for trench dynamic random access memory (DRAM) device design and characterization, and as a manufacturing test vehicle. A nonaddressable array of trench-capacitor DRAM cells is used for quantification of trench DRAM leakage parameters, storage node parasitic device characterization, and silicon defects. Used with an addressable functional monitor, it is found to be a valuable semiconductor process development vehicle to achieve functionality and cell retention yield for a 4-Mb CMOS DRAM technology