Polymer-based 1 /spl times/ 6 thermooptic switch incorporating an elliptic TIR waveguide mirror

A polymeric 1 /spl times/ 6 thermooptic switch is fabricated and demonstrated. The device utilizes an elliptic total internal reflection waveguide mirror imaging the input channel waveguide onto the first output channel waveguide and a prism-array heating electrode steering the beam to corresponding output channel waveguides. At 1310 nm, 1 /spl times/ 6 switching was demonstrated; the extinction ratios and crosstalks were found to be >20 and -20 dB, respectively. Switching time as low as 4 ms was observed. The device offers the advantage of a single-electrode driving scheme for 1/spl times/N(N>2) switching.     

Crosstalk-minimized polymeric 2/spl times/2 thermooptic switch

A thermooptic 2/spl times/2 switch based on the total internal reflection effect is demonstrated. The device, made of ultraviolet curable fluorinated polymer, has an increased half-branch angle of 5/spl deg/. The purpose of a large half-branch angle is to overcome the volume relaxation phenomenon, which is an intrinsic characteristic of polymers. The device successfully decreases the crosstalk below -40 dB in both the cross and bar states. The fabricated device has a power consumption of only 66 mW in the bar state.     

Integrated folding 4/spl times/4 optical matrix switch with total internal reflection mirrors on SOI by anisotropic chemical etching

A folding rearrangeable nonblocking 4/spl times/4 optical matrix switch was designed and fabricated on silicon-on-insulator wafer. To compress chip size, switch elements (SEs) were interconnected by total internal reflection (TIR) mirrors instead of conventional S-bends. For obtaining smooth interfaces, potassium hydroxide anisotropic chemical etching of silicon was utilized to make the matrix switch for the first time. The device has a compact size of 20/spl times/1.6 mm/sup 2/ and a fast response of 7.5 /spl mu/s. The power consumption of each 2/spl times/2 SE and the average excess loss per mirror were 145 mW and -1.1 dB, respectively. Low path dependence of /spl plusmn/0.7 dB in total excess loss was obtained because of the symmetry of propagation paths in this novel matrix switch.     

Low crosstalk 1/spl times/2 thermooptic digital optical switch with integrated S-bend attenuator

We propose and demonstrate a 1/spl times/2 thermooptic digital optical switch with variable optical attenuators that are integrated with the S-bend waveguides connecting the output of the Y-switch with a standard fiber array. With a total heating power of 140 mW applied to the switch, we have achieved less than -42-dB optical crosstalk. The wavelength response of the switch is flat across the entire C-band. The average polarization-dependent loss of the switch is about 0.49 dB.     

Polymer waveguide thermooptic switch with low electric powerconsumption at 1.3 μm

A polymer waveguide thermooptic 2×2 switch with low electric power consumption is demonstrated. The switch consists of a Mach-Zehnder interferometer with Cr thin-film heaters. The waveguides are fabricated using acrylic polymers synthesized from deuterated methacrylate and deuterated fluoromethacrylate monomers. The total insertion loss of the switch is 0.6 dB at a wavelength of 1.3 μm, including fiber coupling losses and waveguide losses. The switching power is as low as 4.8 mW, and the rise and fall times are both 9 ms     

Extremely low loss 4*4 GaAs/AlGaAs optical matrix switch

A 4*4 GaAs/AlGaAs optical matrix switch with an extremely low loss of 1.6 dB has been developed. This low loss switch was achieved by layer structure modification, to reduce free-carrier absorption, reduction of plasma damage while dry etching, and an improvement in the crystal quality.<>     

8/spl times/8 optical switch matrix using generalized Mach-Zehnder interferometers

We report an 8/spl times/8 strictly nonblocking optical cross connect (OXC) using multimode imaging (MMI)-based generalized Mach-Zehnder (MZ) interferometers realized in the silica-on-silicon planar waveguide system. Employing a router-selector architecture, this MMI-MZ OXC design results in a significantly smaller device than conventional directional-coupler based implementations. An average insertion loss of 6 dB and crosstalk of -34 dB, is demonstrated for the 8/spl times/8 OXC.     

Low loss and high extinction ratio strictly nonblocking 16×16thermooptic matrix switch on 6-in wafer using silica-based planarlightwave circuit technology

We describe a silica-based 16×16 strictly nonblocking thermooptic matrix switch with a low loss and a high extinction ratio. This matrix switch, which employs a double Mach-Zehnder interferometer (MZI) switching unit and a matrix arrangement to reduce the total waveguide length, is fabricated with 0.75% refractive index difference waveguides on a 6-in silicon wafer using silica-based planar lightwave circuit (PLC) technology. We obtained an average insertion loss of 6.6 dB and an average extinction ratio of 53 dB in the worst polarization case. The operating wavelength bandwidth completely covers the gain band of practical erbium-doped fiber amplifiers (EDFAs). The total power consumption needed for operation is reduced to 17 W by employing a phase-trimming technique which eliminates the phase-error in the interferometer switching unit     

New radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) and radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) DIF FFT algorithms for 3-D DFT

In this paper, new three-dimensional (3-D) radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) and radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) decimation-in-frequency (DIF) fast Fourier transform (FFT) algorithms are developed and their implementation schemes discussed. The algorithms are developed by introducing the radix-2/4 and radix-2/8 approaches in the computation of the 3-D DFT using the Kronecker product and appropriate index mappings. The butterflies of the proposed algorithms are characterized by simple closed-form expressions facilitating easy software or hardware implementations of the algorithms. Comparisons between the proposed algorithms and the existing 3-D radix-(2/spl times/2/spl times/2) FFT algorithm are carried out showing that significant savings in terms of the number of arithmetic operations, data transfers, and twiddle factor evaluations or accesses to the lookup table can be achieved using the radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) DIF FFT algorithm over the radix-(2/spl times/2/spl times/2) FFT algorithm. It is also established that further savings can be achieved by using the radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) DIF FFT algorithm.     

1/spl times/2 and 1/spl times/4 electrooptic switches

We describe the design, fabrication, and testing of two packaged electrooptic switches built from poled LiTaO/sub 3/ crystals. The 1/spl times/2 switch requires a driving voltage of 1200 V and exhibits insertion loss of 2.4 dB and crosstalk of -39.2 dB; the 1/spl times/4 switch exhibits insertion loss and crosstalk of 2.8 dB and -40.6 dB, respectively, and operates using a 1100-V voltage source. The maximum deflection time between the channels is 86 ns.     

1100 /spl times/ 1100 port MEMS-based optical crossconnect with 4-dB maximum loss

We present a microelectromechanical systems-based beam steering optical crossconnect switch core with port count exceeding 1100, featuring mean fiber-to-fiber insertion loss of 2.1 dB and maximum insertion loss of 4.0 dB across all possible connections. The challenge of efficient measurement and optimization of all possible connections was met by an automated testing facility. The resulting connections feature optical loss stability of better than 0.2 dB over days, without any feedback control under normal laboratory conditions.     

1/spl times/4 optical switch based on transversal filter configuration with constant power consumption

An optical switch based on a transversal filter configuration is demonstrated. The switch consists of cascaded 3 dB optical power splitters and a phase shifter array. By using a silica-based planar lightwave circuit, a 1/spl times/4 optical switch was realised. A characteristic of the switch is that its power consumption is constant regardless of the output selection.     

Characterization of 1/spl times/N broadcast and 2/spl times/N multicast packet switching using active-vertical-coupler-based optical crosspoint switch

This paper reports the expansion of a novel optical multicast scheme to 1-to-4 and 2-to-4 configurations using an active-vertical-coupler (AVC)-based optical crosspoint switch (OXS) matrix. A 1-to-4 broadcast experiment has been carried out first, with only 0.5 dB excess loss per signal split. Input signals with two wavelengths are then fed into one row of OXS to investigate the effect of wavelength-division multiplexing on the 1-to-4 multicast switching. Finally, combining both, the expanded 2-to-N multicast is also achieved with an N value up to 4. The switching characteristics, switched signal quality, and optical signal-to-noise ratio (OSNR) have been investigated in different configurations. Power penalties of less than 4.5 dB are found in worst case switched signals in the 2-to-4 configuration. Slow OSNR degradation in line with previous prediction is also observed. The measured results confirm the excellent multicast switching characteristics nearly free from power splitting loss in this device.     

Optimizing imbalance and loss in 2 /spl times/ 2 3-dB multimode interference couplers via access waveguide width

The imbalance and excess loss in multimode interference couplers with fabrication errors are examined. Remarkably, there exists a number of optimum access waveguide widths which give a minimum imbalance. Furthermore, quite low excess loss can be simultaneously achieved by choosing one particular optimum width. It is also shown that paired interference couplers have better imbalance performance than general interference couplers, given the same fabrication tolerances and length constraint for both coupler types. In particular, a paired interference coupler with an access waveguide width approximately 0.3 times the coupler width has the best imbalance performance. These results are obtained using a simple model and are supported by more sophisticated numerical models and experimental data from couplers fabricated in InP/InGaAsP.     

一种高隔离度低损耗CMOS射频收发开关设计方法

本文采用了LC并联谐振的办法设计了高性能的CMOS收发开关,由于消除了CMOS晶体管的寄生电容的影响,降低了开关电路的插入损耗、提高隔离性能。同时利用直流偏置和交流浮动技术来提高开关的功率容纳能力。采用TSMC0.35 m RF-CMOS工艺设计的收发开关,模拟结果表明谐振频率工作点的插入损耗为1.03dB,收发端隔离39.277dB,输入1dB压缩点(P1dB)功率26.28dBm。     

A 4K/spl times/8 dynamic RAM with self-refresh

A 4K/spl times/8 MOS dynamic RAM using a single transistor cell with on-chip self-refresh is described. The device uses a multiplexed address/data bus. Control of the reconfigurable data bus allows the RAM to operate on either an 8-bit or a 16-bit data bus. The memory cell is fabricated using a double polysilicon n-channel HMOS technology using polysilicon word lines and metal bit lines. Self-refresh is implemented with an on-chip timer, arbiter, counter and multiplexer. A high-speed arbiter resolves simultaneous memory and refresh requests. Redundant rows are used for increased manufacturing yields. Polysilicon fuses are electrically programmed to select redundant rows.     

A 50-/spl mu/A standby 1M/spl times/1/256K/spl times/4 CMOS DRAM with high-speed sense amplifier

A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.     

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMICfront-end with a low insertion loss switch

This paper describes the design and experimental results of a 1.8-V single-chip CMOS MMIC front-end for 2.4-GHz band short-range wireless communications, such as Bluetooth and wireless LANs. The IC consists of fundamental RF building circuits-a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive-antenna switch (SW), including almost all on-chip matching elements. The IC was fabricated using a 0.18-μm standard bulk CMOS technology which has no extra processing steps to enhance the RF performances. Two new circuit-design techniques are introduced in the IC in order to minimize the insertion loss of the SW and realize a higher gain for the PA and LNA despite the utilization of the standard bulk CMOS technology. The first is the derivation of an optimum gate width of the SW to minimize the insertion loss based on small-signal equivalent circuit analysis. The other is the revelation of the advantages of interdigitated capacitors (IDCs) over conventional polysilicon to polysilicon capacitors and the successful use of the IDCs in the LNA and PA. The IC achieves the following sufficient characteristics for practical wireless terminals at 2.1 GHz and 1.8 V: a 5-dBm transmit power at a -1-dB gain compression, a 19-dB gain, an 18-mA current for the PA, a 1.5-dB insertion loss, more than 24-dB isolation, an 11-dBm power handling capability for the SW, a 7.5-dB gain, a 4.5-dB noise figure, and an 8-mA current for the LNA     

Calculation of CFIE impedance matrix elements with RWG and n/spl times/RWG functions

The method of moments (MoM) solution of combined field integral equation (CFIE) for electromagnetic scattering problems requires calculation of singular double surface integrals. When Galerkin's method with triangular vector basis functions, Rao-Wilton-Glisson functions, and the CFIE are applied to solve electromagnetic scattering by a dielectric object, both RWG and n/spl times/RWG functions (n is normal unit vector) should be considered as testing functions. Robust and accurate methods based on the singularity extraction technique are presented to evaluate the impedance matrix elements of the CFIE with these basis and test functions. In computing the impedance matrix elements, including the gradient of the Green's function, we can avoid the logarithmic singularity on the outer testing integral by modifying the integrand. In the developed method, all singularities are extracted and calculated in closed form and numerical integration is applied only for regular functions. In addition, we present compact iterative formulas for computing the extracted terms in closed form. By these formulas, we can extract any number of terms from the singular kernels of CFIE formulations with RWG and n/spl times/RWG functions.     

A fast 32 K/spl times/8 CMOS static RAM with address transition detection

A high-speed 256 K (32 K/spl times/8) CMOS static RAM (SRAM) is described. Precharging and equalization schemes are implemented with address-transition-detection (ATD) techniques. With a differential sensing circuitry, a 23-ns access time is achieved (at V/SUB cc/=5 V and 25/spl deg/C) for addresses and chip-select clocks. The operating current is 36 mA in the READ cycle and 28 mA in the WRITE cycle, at 10-MHz cycling frequency. A four-transistor memory cell is designed with double-polysilicon and double -metal layers to achieve high performances. Versatile redundancy schemes consisting of polysilicon laser fuses, logical circuitry, and novel enable/disable controls are designed to repair defective cells. A compensation circuit is used to optimize writing parameters for redundant columns.