Fabrication and characterization of bipolar transistors within-situ doped low-temperature (800°C) epitaxial silicon

The authors report the fabrication of bipolar transistors at a maximum process temperature of 800°C, utilizing in situ doped low-temperature epitaxial silicon deposited by ultralow-pressure chemical vapor deposition (U-LPCVD), and their subsequent characterization. The epitaxial silicon layers form the collector, base, and emitter layers. To attain a high donor concentration in the epitaxial emitter layer, the U-LPCVD process is plasma enhanced. Transistors having excellent DC characteristics down to collector currents of ~10 pA/μm² are obtained, which indicates that the bulk quality of the epitaxial films is good enough for device fabrication     

Bipolar transistor fabrication in low-temperature (745°C) ultra-low-pressure chemical-vapor-deposited epitaxial silicon

In this letter we report for the first time the successful fabrication of bipolar transistors in low-temperature (Tdep= 745°C) epitaxial silicon deposited by a chemical-vapor-deposition (CVD) technology. The epitaxial layers were deposited by an ultra-low-pressure CVD (U-LPCVD) technique utilizing an optimized in-situ predeposition argon sputter clean. The critical parameter during the sputter clean has been identified as the substrate bias. Bias voltages of -200 or -300 V create dislocations that form emitter-collector shunts during the bipolar transistor fabrication process; a bias voltage of -100 V, however, permits the deposition of essentially defect-free (<10 dislocations cm^-2by defect etching) epitaxial films suitable for bipolar transistor fabrication.     

Electrical characterization of heavily doped polycrystalline silicon for high-frequency bipolar transistor application

Electrical conduction data from heavily doped p-type polysilicon thin films at room temperature and above are presented. Specifically, the sheet resistance, in the range from 1 kΩ/□ to 100 Ω/□ for a doping level of 10¹⁹cm^-3to 10²⁰cm^-3, is characterized over temperatures from 300 to 450 K. It is shown that the polysilicon resistivity, larger than the corresponding crystalline value by a factor ∼ 10, is flat over the entire temperature range used for measurement. This large resistivity is correlated to the degree of dopant activation and the mobility in polysiUcon. The measured mobility varying from 8 to 20 cm²/V . s is shown to be smaller than the crystalline mobility at the same doping level by a factor 7 ∼ 3. These data are comprehensively discussed and quantified, based on a distributed resistivity model.     

Growth and characterization of germanium and boron doped silicon epitaxial films

The epitaxial growth and characterization of in-situ germanium and boron (Ge/B) doped Si epitaxial films is described. As indicated by secondary ion mass spectroscopy and spreading resistance measurements, the total and electrically activated B concentrations are essentially identical and independent of Ge incorporation. The B and Ge concentrations are uniformly distributed in these Ge/B doped films. A slight enhancement of Hall mobility is obtained, possibly due to the stress relief induced by Ge counterdoping. Carrier conduction in these films is due to the activated B with an activation energy of 0.04 eV as revealed by conductivity versus temperature measurements. Ge atoms appear to be isoelectronic with Si atoms in these films. A slight degradation of minority carrier diffusion length is observed. Electrical characterization of PN diodes on these Ge/B doped films do not reveal any anomaly. SiO₂ on these Ge/B doped films has similar oxide fixed charge density, interface state density and dielectric breakdown strength compared to silicon dioxide on boron doped epitaxial films. Electron injection reveals a different transport mechanism of the SiO₂ grown on these Ge/B doped films.     

Electrical characterization and modelling of high energy pre-amorphized PN silicon junctions

Shallow P⁺N junctions were obtained using germanium pre-amorphization step to reduce the high diffusivity of boron implanted in silicon. The germanium implantation step was performed under different conditions of temperature: ambient temperature and nitrogen temperature. P-type doping was obtained by boron implantation at relatively low energy. To characterize and simulate the electrical behaviour of such samples, steady state current-voltage measurements have been performed at different temperatures varying between 172 and 294 K. The results show a close dependence between the current-voltage characteristics of the samples and their technological parameters of manufacturing. The pre-amorphization step at ambient temperature seems to improve the electrical behaviour of the junction. To simulate the electrical characteristics of the studied samples, a reliable model has been developed based on the classical Spice formulas and taking into account additional phenomena. The simulated curves satisfactorily fit the experimental results for all the samples.     

Cross-sectional TEM characterization of low temperature (750-800°C) epitaxial silicon by very low pressure (6 mTorr) chemical vapor deposition with and without plasma enhancement

Cross-sectional transmission electron microscopy (XTEM) and high resolution transmission electron microscopy (HRTEM) were used to characterize epitaxial silicon grown by chemical vapor deposition at 750–800° C. Optimum conditions for pre-deposition argon plasma sputter cleaning were found to be -100 V dc substrate bias and 2.5 W rf power for 13 minutes at 4 m Torr and 750–800° C. No dislocations were observed by XTEM in films deposited subsequent to this plasma exposure. Analysis of the epitaxial layer/substrate interface by HRTEM indicates complete lattice registration despite the presence of a discontinuous array of defects or microprecipitates. The strain field associated with these defects is approximately 13Å in width. Annealing the epitaxial layers at 1150° C inN ₂ for 4 hours led to the generation of additional defects believed to be associated with carbon and oxygen clustering. Preliminary results indicate that neither temporary (30 seconds) growth interruptions nor low power (2.5 W) plasma enhancement of thedeposition process lead to the generation of defects observable by XTEM.     

In situ temperature measurement by infrared absorption for low-temperature epitaxial growth of homo- and hetero-epitaxial layers on silicon

The use of infrared transmission to measure silicon wafer temperature in a lamp-heated susceptor-free reactor is described. The relevant temperature range is 400 to 800° C, and the accuracy is on the order of a few degrees centigrade. The method is then applied towards the growth of silicon and silicon-germanium alloy layers on silicon substrates. For silicon-germanium layers typical of those used in heterojunction bipolar transistors, no change in absorption compared to that of the silicon substrates is observed.     

Application of selective epitaxial silicon and chemo-mechanicalpolishing to bipolar transistors

Successful demonstration of single-polysilicon bipolar transistors fabricated using selective epitaxial growth (SEG) and chemo-mechanical polishing (CMP) is reported. The pedestal structure made possible by the SEG/CMP process combination results in significantly reduced extrinsic-base collector capacitance. Cut-off frequency (f_T) of devices with emitter stripe width of 1 μm, a base width of 110 nm, and a peak base doping of 3×10¹⁸ cm^-3 have been observed to improve from 16 GHz to 22 GHz when the extrinsic-base collector overlap is decreased from 1 μm to 0.2 μm. Leakage current, often a problem for SEG structures, has been reduced to 27 nA/cm² for the area component, and 10 nA/cm for the edge component, by (1) appropriate post-polish processing, including a high-temperature anneal and sacrificial oxidation, (2) aligning the device sidewalls along the 〈100〉 direction, and (3) the presence of the pedestal structure. Base-emitter junction nonideality in these transistors has also been investigated     

Electrical characterization of epitaxial silicon deposited at low temperatures by plasma-enhanced chemical vapor deposition

The initial results of an investigation of the electrical properties of epitaxial silicon films deposited at low temperatures (i.e., 750°C) by the Plasma-Enhanced Chemical Vapor Deposition (PECVD) technique are presented. The major results indicate that (1) the electron and hole drift mobilities in the epitaxial layers are the same as in bulk silicon for carrier concentrations between 10¹⁷cm^-3and 10¹⁹cm^-3, and (2) high quality p-n junction diodes with no sign of soft breakdown and an ideality factor of 1.10 are obtained at an epitaxial deposition temperature of only 750°C. These p-n diodes represent the first ever reported IC devices fabricated in PECVD epitaxial films.     

Electrical characterization of p+/n shallow junctions obtained by boron implantation into preamorphized silicon

Electrical characteristics of p⁺/n diodes obtained by boron implantation into amorphous silicon layers formed by a prior implantation of Si⁺ ions are presented. The absence of channeling phenomena (preamorphization), the low boron implantation energy (10–20 keV), and the post-implantation low temperature anneal (600–1000°C) or rapid anneal (electron beam) allow to obtain very shallow junctions (0.1–0.3 μm). Particular attention is given to analyse effects on the reverse diode current from dislocation loops which are formed at the amorphous-crystalline interface during annealing. If the dislocation loops are outside of the space charge region, the diodes show a low leakage current (∼ 1 nA/cm² at - 1 v), but the reverse current increases strongly when this residual damage falls into the depleted n-region. Experimental I–V characteristics are in excellent agreement with a numerical simulation, which takes into account a strong lifetime degration associated with the dislocation loops.     

A temperature-dependent SOI MOSFET model for high-temperatureapplication (27 °C-300 °C)

A temperature-dependent model for long-channel silicon-on-insulator (SOI) MOSFETs for use in the temperature range 27 °C-300 °C, suitable for circuit simulators such as SPICE, is presented. The model physically accounts for the temperature-dependent effects in SOI MOSFETs (such as threshold-voltage reduction, increase of leakage current, decrease of generation due to impact ionization, and channel mobility degradation with increase of temperature) which are influenced by the uniqueness of SOI device structure, i.e. the back gate and the floating film body. The model is verified by the good agreement of the simulations with the experimental data. The model is implemented in SPICE2 to be used for circuit and device CAD. Simple SOI CMOS circuits are successfully simulated at different temperatures     

Charge-packet-initiated switching of metal—tunnel-oxide—silicon (MTOS) junctions

We report the switching of a bistable metal-tunnel-oxide-silicon (MTOS) junction from a low-current state to a high-current state by the insertion of a charge packet of minority carriers from a charge-coupled device input structure. For the 33-Å tunnel oxide reported in this letter, a switching threshold of 630 pC for a 40 mils²device area was observed. The transient switching time is approximately 10-100 ms, depending upon the size of the injected charge packet.     

Low-temperature (⩽550°C) fabrication of poly-Si thin-filmtransistors

High performance n- and p-channel thin-film transistors (TFTs) have been fabricated in polycrystalline silicon films using a self-aligned-gate process without exceeding 550°C. This process features the use of polycrystalline Si_0.5Ge_0.5 for the gate material and high-dose H⁺ implantation for grain-boundary passivation so that shorter process times can be used. Low threshold voltages of 2.8 and -0.2 V, and high field-effect mobilities of 35 and 28 cm²/V-s, where achieved by the NMOS and PMOS devices, respectively. The performance of these devices is comparable to that of previously reported devices fabricated using process temperatures up to 600°C, and is adequate for large-area-display peripheral driver circuits. The significant reduction in maximum process temperature makes this process advantageous for the fabrication of CMOS circuits on large-area glass substrates     

Terahertz-radiation generation in low-temperature InGaAs epitaxial films on (100) and (411) InP substrates

The spectrum and waveforms of broadband terahertz-radiation pulses generated by low-temperature In_0.53Ga_0.47As epitaxial films under femtosecond laser pumping are investigated by terahertz time-resolved spectroscopy. The In_0.53Ga_0.47As films are fabricated by molecular-beam epitaxy at a temperature of 200°C under different arsenic pressures on (100)-oriented InP substrates and, for the first time, on (411)A InP substrates. The surface morphology of the samples is studied by atomic-force microscopy and the structural quality is established by high-resolution X-ray diffraction analysis. It is found that the amplitude of terahertz radiation from the LT-InGaAs layers on the (411)A InP substrates exceeds that from similar layers formed on the (100) InP substrates by a factor of 3–5.     

MBE growth and characterization of in situ arsenic doped HgCdTe

We report the results of in situ arsenic doping by molecular beam epitaxy using an elemental arsenic source. Single Hg_1−xCd_xTe layers of x ∼0.3 were grown at a lower growth temperature of 175°C to increase the arsenic incorporation into the layers. Layers grown at 175°C have shown typical etch pit densities of 2E6 with achievable densities as low as 7E4cm⁻². Void defect densities can routinely be achieved at levels below 1000 cm⁻². Double crystal x-ray diffraction rocking curves exhibit typical full width at half-maximum values of 23 arcsec indicating high structural quality. Arsenic incorporation into the HgCdTe layers was confirmed using secondary ion mass spectrometry. Isothermal annealing of HgCdTe:As layers at temperatures of either 436 or 300°C results in activation of the arsenic at concentrations ranging from 2E16 to 2E18 cm⁻³. Theoretical fits to variable temperature Hall measurements indicate that layers are not compensated, with near 100% activation after isothermal anneals at 436 or 300°C. Arsenic activation energies and 77K minority carrier lifetime measurements are consistent with published literature values. SIMS analyses of annealed arsenic doping profiles confirm a low arsenic diffusion coefficient.     

Growth and characterization of Si doped vapor phase epitaxial GaAs for mesfet

This paper describes the Si-doping of GaAs that was grown using the AsCl₃:H₂:GaAs, Ga Chemical vapor deposition process. The doping sources were AsCl₃:SiCl₄ liquid solutions which proved to be highly reproducible for Si doping within the range, 1×1O¹⁶ to 2×10¹⁹ cm^?3. Incorporation of Si into the GaAs apparently occurs under near equilibrium conditions. This point is considered in detail and the consequences experimentally utilized to grow n, n+ bilayers using a single AsCl₃:SiCl₄ doping solution. Si impurity profiles based upon differential capacitance and SIMS data are presented. These can be very abrupt for n, n⁺ structures with order of magnitude changes occurring within 500 Å. For the 1×10₁₆ to 8×l0¹⁸ cm^?3 doped samples the mobilities at 78 and 298°K are comparable to the higher values reported for GaAs thin films grown by CVD. Power FET devices made from this material have demonstrated an output density of 0.86 watts/mm at 10 GHz.     

Room temperature (34°C) operation of strain-compensated quantumcascade lasers

A short wavelength (λ-3.5 μm) strain-compensated In_xGa_(1-x)As/In_yAl_(1-y)As quantum cascade laser is reported. Quasi-continuous wave operation of this device at 34°C with an output power of 11.4 mW persisted for more than 30 minutes without obvious degradation. A very low threshold current density of 1.2 KA/cm² at this temperature was observed     

Electrical characteristics of scaled CMOSFET's with source/drainregions fabricated by 7° and 0° tilt-angle implantations

The differences of electrical characteristics in trench-isolated n-well CMOSFET's with LDD- and EPS-regions fabricated by 7° and 0° tilt-angle phosphorous implantations are measured and qualitatively explained. The CMOSFET's have channel lengths ranging from 5 to 0.4 μm and a channel width of 10 μm. The differences in impurity profiles due to the channeling ions by 0°-implantation cause the clear changes in the punchthrough-current characteristics and the substrate bias-voltage dependences of threshold voltages for both n- and p-MOSFET's. Meanwhile n- and p-MOSFET's fabricated by 7° and 0° implantations show nearly the same characteristics of threshold voltages and subthreshold swings which are almost determined by the impurity profiles in each channel region because the impurity profiles are scarcely affected by the channeling ions     

High-temperature electrical characteristics of GaAs MESFETs(25-400°C)

The effects of elevated ambient and substrate temperatures (25°C up to 400°C) on the electrical characteristics of integrated GaAs MESFETs in a state-of-the-art commercial technology are reported. The focus is on the large- and small-signal parameters of the transistors. The existence of zero-temperature-coefficient drain currents is demonstrated analytically and experimentally for enhancement- and for depletion-mode GaAs MESFETs. The data show that, while GaAs MESFETs generally display degradation mechanisms similar to those of silicon MOSFETs with increasing temperature, they incur several additional effects, prominent among which are increased gate leakage currents, lowered Schottky-barrier height, decreased large- and small-signal (gate) input resistances, decreased sensitivity to sidegating and backgating up to approximately 200°C, and increased small-signal drain resistance     

Transport equations in heavily doped silicon,and the current gain of a bipolar transistor

The Fermi level and effective density of states are calculated for heavily doped silicon, using methods similar to those of Kleppinger and Lindholm and Van Overstraeten et al. For the case in which Boltzmann statistics can be applied to both types of carriers, modified transport equations are obtained in terms of two “heavy doping parameters,” which measure the magnitude and skewness of the effective forbidden band.These results are applied to the calculation of the d.c. current gain of a diffused bipolar transistor. We obtain reasonable current gain values without employing short carrier lifetimes, and our numerically calculated dependence of the current gain on injection level is reasonable. However, the quantitative accuracy of our calculations is limited by several factors.