A simple wafer-level measurement technique for predicting oxidereliability

A new wafer-level measurement technique, the differential gate antenna analysis, has been developed to detect weaknesses in sub-micrometer oxide. This simple technique involves the use of dual antenna structures with different gate oxide areas but the same antenna area ratio. The critical parameter is the difference in their failure levels. It is shown that such a differential measurement of antenna failures correlates with product failure during accelerated life testing. The differential antenna structures are thus proven useful for real-time wafer-level monitoring of oxide reliability     

Experimental study of the quasi-breakdown failure mechanism in 4.5 nm-thick SiO2 oxides

In this study, we have investigated the electrical properties of the failure mode referred as quasi-breakdown or soft-breakdown in MOS capacitors on p-type substrate with an oxide thickness of 4.5 nm. Quasi-breakdown appears during high field stresses as a sudden increase between two and four orders of magnitude in the gate current over the whole gate voltage range, but remains undetected in C(V) characteristics between 20 Hz and 100 kHz. Quasi-breakdown was systematically triggered during negative gate voltage stresses after a threshold between 10 and 15 C/cm² was reached in the injected charge, this threshold being independent of the stressing oxide field. A very weak temperature dependence and a low frequency noise in the gate current were also observed. The I(V) characteristics are found to follow a first-order exponential law versus the gate voltage, indicative of a direct tunneling process, which could result from a local lowering of the oxide thickness resulting from a sudden metal/isolant transition in a localized region of the oxide near the anode due to oxide defects.     

Compact failure modeling for devices subject to electrostatic discharge stresses – A review pertinent to CMOS reliability simulation

This paper reviews the physical mechanisms and compact modeling approaches of two physical damages in MOS devices induced by electrostatic discharge (ESD) stresses; namely gate oxide breakdown and thermal failures. Theories underlying the failure mechanism are discussed and compact models that can be used to monitor ESD induced gate oxide breakdown and thermal failure are developed. Related work reported in the literature is discussed, and benchmarking of measurement data versus simulation results are included in support of the modeling work.     

Recoverable ionic contaminant induced failures on n-channel memory products

For an n-channel MOSFET device technology, thick oxide threshold voltage degradation on a device adjacent to a thin oxide device with exposed gate oxide and tapers frequently causes chip failure. If the thin gate oxide and tapers are completely covered, then threshold voltage stability can be attained using phosphosilicate glass to getter ionic contaminants. A first order theory is proposed that relates circuit topology, electrical requirements, and ionic contaminant drift in oxides to chip failure. The model predicts the hierarchy of failing circuits within a chip and the recovery of these failures when left on temperature-bias testing. The latter implies that burn-in conditions must be carefully chosen to avoid recovery during temperature-bias testing. Failure to do so will allow this failure mode to go undetected and result in overly optimistic reliability projections for application conditions.     

Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study

A CMOS ring oscillator circuit is observed to operate even after a number of its FET's have undergone a hard gate oxide breakdown. The first breakdown is identified with emission microscopy and statistical tools to most likely occur in the circuit's nFET's. A physical model and an equivalent electrical circuit for an nFET after hard gate oxide breakdown are constructed and used to confirm the understanding of the impact of FET gate oxide breakdown on the ring oscillator. The observations are generalized to conclude that, provided stable soft breakdowns are the only gate oxide failures occurring at operating conditions, large parts of digital CMOS circuits will be unaffected by these failures.     

Reproducibility of field failures by ESD models — Comparison of HBM, socketed CDM and non-socketed CDM

Two types of IC's with field failures explainable only by ESD damage could be identified. A comparative study with failures caused by HBM, socketed CDM and non-socketed CDM clearly shows, that the failure type of one IC could only be simulated with CDM stress. Socketed as well as non-socketed CDM reproduced exactly the same gate oxide damage at one edge of a specific input transistor as it is known by field failure analysis. Although similar threshold voltages are not expected for both kinds of CDMs because of their different discharge pulse forms, in this case they are found to be almost equal.     

An approach to statistical analysis of gate oxide breakdown mechanisms

A credible statistical algorithm is required to determine the parameters of the bimodal Weibull mixture distribution exhibited by the gate oxide breakdown phenomenon, consisting of extrinsic early-life defect-induced failures and intrinsic wear-out failure mechanisms. We use a global maximization algorithm called simulated annealing (SA) in conjunction with the expectation–maximization (EM) algorithm to maximize the log-likelihood function of multi-censored gate oxide failure data. The results show that the proposed statistical algorithm provides a good fit to the stochastic nature of the test failure data. The Akaike information criterion (AIC) is used to verify the number of failure mechanisms in the given set of data and the Bayes’ posterior probability theory is utilized to determine the probability of each failure data belonging to different failure mechanisms.     

Mechanisms of positive gate-bias stress induced instabilities in CMOS transistors

Increase of positive gate oxide charge and interface trap densities has been shown to be responsible for positive gate-bias stress induced instabilities of threshold voltage and gain factor in Al-gate and Si-gate CMOS transistors. The electron tunneling from trivalent-silicon and/or oxygen-vacancy defects into the oxide conduction band has been established as a mechanism of the positive gate oxide charge creation. The creation of interface traps, appearing due to interfacial trivalent silicon atoms, has been related to the reaction between interfacial Si-H or Si-OH groups and the positive gate oxide charge built up close to the oxide-silicon interface.     

Prognostic methodology for deep submicron semiconductor failuremodes

Semiconductor reliability issues are beginning to emerge as a major impediment to long term reliability of critical systems such as Internet routers, ATM machines, and Automotive/Aerospace fly-by-wire systems. Semiconductors have certain defined failure modes that can contribute to end-of life failures. These modes include time-dependent dielectric breakdown of the gate oxide (TDDB), hot carrier damage, and metal migration. All of these common failure modes are far worse at geometries below 0.25 μm. Fortunately, there are methods proposed that counteract these common failure modes. This paper surveys the problems involved, and recommends a methodology for the inclusion of pre-calibrated prognostic cells that can be co-located with a host circuit to provide an “early-warning” of a system failure, so that appropriate corrective action can be taken     

Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation

This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills the interface of poly-Si grains and repairs the poly-Si film damaged by source–drain (S/D) implantation. The plasma-induced damage (PID) effect is observed and SRO can also suppress this PID effect and, thus, enhance GOI process margin. This is because PID may be enhanced during plasma poly-Si etching and S/D implantation, which induces the under-layer latent defects and deteriorates the adhesion between poly-grains and oxide. The SRO refraction index, which is 1.56 in this study with maximum silane (SiH₄) in cap oxide furnace, was found to play an important role on eliminating poly-holes. In-line SEM inspections show that poly-Si holes happen at open area such as the GOI test patterns of large bulk area and of poly-Si edge. Therefore, in-line defect inspections, which usually check only cell area, fail to find poly-Si holes. Hence, the in-line GOI monitor is proposed to detect such “hidden” defects. In this paper, we found SRO can successfully eliminate poly-Si holes, which lead to GOI failures, with minimum productivity loss and negligible process costs. Since GOI monitor by V-Ramp test is implemented to detect such reliability failure, wafer-level reliability control is recommended to proactively monitor and improve GOI performance. In order to achieve more stringent reliability targets as technology marches to the 0.10 μm era, we introduce the concepts of build-in reliability to facilitate qualifications and to incorporate related/prior reliability concerns for developing advanced processes.     

Radical Modification of Gate Oxide by Lateral Gettering of Electroactive Centers

An approach to radically modifying gate dielectric by laterally gettering electroactive defects (centers) is suggested. Gettering of the ionized centers is accomplished through intentionally creating structure defects in the surface layers of the side oxide that are adjacent to the periphery of the gate oxide. The process was carried out at low temperatures, e.g., during postmetallization annealing in a hydrogen-free atmosphere. The structure defects in the side oxide capture excessive hydrogen, which otherwise produces ionized donors in the gate oxide layer. If the gate size is comparable to the hydrogen diffusion length (5–10 m), ionized acceptor centers of concentration no more than 10¹¹ cm^–2 dominate in the gate oxide after annealing. This is apparently related to the minimization of excessive hydrogen content in the gate oxide of structures with small lateral dimensions.     

Post-irradiation formation of Si-SiO2 interface states in a hydrogen atmosphere at room temperature

Si MOSFETs were irradiated with x-rays and then exposed to various partial pressures of H₂ at either room temperature or 125 °C. The number of interface traps and the net positive oxide trapped charged were measured during the hydrogen exposure using spectroscopic charge pumping techniques. During the hydrogen exposure the gate electrode was held at a positive bias to maintain a field of 0.65 MV/cm across the gate oxide. It was found that during the room temperature hydrogen exposure the number of interface traps increased by a factor of about two. The change in the oxide trapped charge during hydrogen exposure indicated that the decrease in the number of positively charged oxide traps was approximately the same as the increase in the number of interface traps. The time evolution and bias dependence of these changes are explained by a model that we previously proposed. In this model positively charged radiation induced defects in the oxide crack the H₂ to form H⁺. Under positive gate bias the H⁺ then drifts to the Si-SiO₂ interface where it forms an interface state, while at the same time removing positive charge from the oxide.     

Evaluation of performance–reliability trade-offs in a Si–Ge BiCMOS process using fast wafer level techniques

Fast wafer-level reliability (fWLR) techniques are successfully implemented in order to investigate several gate oxide reliability–performance tradeoffs that affect the architecture of a high speed BiCMOS process. Fast feedback of device and reliability parameters is required during process development in order to avoid failures during process qualification. This study highlights some performance–reliability tradeoffs that had to be overcome during the development of a modern BiCMOS process.     

Impact of ESD-induced soft drain junction damage on CMOS product lifetime

The impact of ESD-induced soft drain junction damage on product lifetime was investigated. Several thousand input-output (IO) pads of a 0.35 pm CMOS IC were stressed by ESD (electrostatic discharge) and subsequently subjected to bakes, ESD re-stress and high temperature operating life tests. While the ESD-induced soft drain junction damage appears to be stable versus temperature stress and ESD-re-stress, it results in early failures during accelerated operating life tests. These lifetest failures are caused by breakdown of the gate oxide which was left unbroken during the ESD stress that caused the ESD-induced soft drain junction damage. Thus, ESD-induced soft drain junction damage might cause a reliability risk (latent ESD failure). Consequently, it needs to be avoided by assuring a sufficient robustness of the IC against this ESD damage mechanism. A leakage current criterion of I VA is rather large to detect this kind of damage after ESD stress.     

220kV变电站中刀闸接触缺陷对断路器保护的影响

以一例220kV变电站中出现的刀闸接触缺陷为背景,分析这种缺陷与断路器保护之间存在的关系.文章发现在刀闸接触存在缺陷期间,失灵保护功能与死区保护功能均无法在断路器中得以正常运行,正确动作失真,如无妥善解决,则可能引发事故的进一步扩大.为解决刀闸接触缺陷问题,本文提出具体解决措施,以杜绝此类问题再次出现.     

ESD protection for thin gate oxides in 65 nm

Unexpected functional failures were found in the core of an IC, processed in a 65 nm technology with 1.8 nm gate oxide, after Machine Model (MM) testing, although a comprehensive rail-based protection scheme was applied. Failure analysis was performed including Obirch, backside de-processing, and SEM analysis to locate the failure in the gate oxide of several core NMOS transistors. Careful Transmission Line Pulse (TLP) measurements on NMOSTs with 1.8 nm oxides yields a mean BVox = 6.06 V and standard deviation of 0.18 V, after correction for MM test conditions. Comparison with a mean Vt1 = 5.35 V and a standard deviation of 0.15 V for ggNMOSTs shows that the tails of the BVox and Vt1 distributions overlap. This implies that connecting a gate to a drain diffusion does not guarantee adequate protection for a 1.8 nm gate oxide in a 65 nm technology.     

Elimination of surface state induced edge transistors in high voltage NMOSFETs for flash memory devices

The abnormal leakage failure in high voltage NMOSFETs is investigated by measuring the subthreshold hump characteristics. Gated diode, width and substrate bias dependence of the I_D-V_GS characteristics, and two-terminal I-V measurements between the source and the drain reveal that the hump characteristic is caused by the surface states, not by the gate field crowding at STI edges. The numerical calculation shows that the high voltage NMOSFETs are very delicate to leakage failure by a small amount of surface state (10¹¹ /cm²), due to the thick gate oxide and very low doping concentration for high voltage operation (>25 V). A thermal oxidation with the thickness of 1.0 nm successfully eliminates the parasitic corner transistors without changing electrical characteristics of the targeted transistors in current state of the art flash memory devices.     

Annealing of radiation-induced positive charge in MOS devices with aluminum and polysilicon gate contacts

This paper discusses the removal of radiation-induced positive charge from MOS structures by low temperature thermal anneals. Results are presented for structures in which the gate oxide is covered either by an aluminum or by a polysilicon contact during the anneal. The anneals were performed in forming gas, nitrogen and hydrogen ambients. The presence of aluminum over the gate oxide is found to play an important role in the annealing of radiation-induced positive charge in these structures . While a 400?C anneal is sufficient to remove this charge from capacit or structures with aluminum gates, it leaves a small amount of residual charge (about 6xl0¹⁰}cm²}) in structures with polysilicon gates. Anneals at temperatures in excess of 550?C are required to remove this charge completely from the polysilicon-gated MOS devices. However when a thin layer of aluminum is present over the polysilicon contact during the anneal the charge can be removed easily at 400?C. The results in capacitor structures are consistent with those found in polysilicon gate MOSFET’s with similar coverage over the gate oxide.     

TLP应力下深亚微米GGNMOSFET特性的仿真

对TLP(传输线脉冲)应力下深亚微米GGNMOS器件的特性和失效机理进行了仿真研究. 分析表明，在TLP应力下，栅串接电阻减小了保护结构漏端的峰值电压；栅漏交迭区电容的存在使得脉冲上升沿加强了栅漏交叠区的电场，栅氧化层电场随着TLP应力的上升沿减小而不断增大，这会导致栅氧化层的提前击穿. 仿真显示，栅漏交迭区的电容和栅串接电阻对GGNMOS保护器件的开启特性和ESD耐压的影响是巨大的. 该工作为以后的TLP测试和标准化提供了依据和参考.     

Physical analysis of breakdown in high-κ/metal gate stacks using TEM/EELS and STM for reliability enhancement (invited)

In this invited paper, we demonstrate how physical analysis techniques that are commonly used in integrated circuits failure analysis can be applied to detect the failure defects associated with ultrathin gate dielectric wear-out and breakdown in high-κ materials and investigate the associated failure mechanism(s) based on the defect chemistry. The key contributions of this work are perhaps focused on two areas: (1) how to correlate the failure mechanisms in high-κ/metal gate technology during wear-out and breakdown to device processing and materials and (2) how the understanding of these new failure mechanisms can be used in proposing “design for reliability” (DFR) initiatives for complex and expensive future CMOS nanoelectronic technology nodes of 22 nm and 15 nm. Hf-based high-κ materials in conjunction with various gate electrode technologies will be used as main examples while other potential high-κ gate materials such as cerium oxide (CeO₂) will also be demonstrated to further illustrate the concept of DFR.