Degradation of double-gate polycrystalline silicon TFTs due to hot carrier stress

Degradation phenomena due to hot carrier stress conditions were investigated in double-gate polysilicon thin film transistors fabricated by sequential lateral solidification (SLS). We varied the hot carrier stress conditions at the front gate channel by applying various voltages at the back-gate. Thus, we investigated the device electrical performance under such stress regimes. As a conclusion, we demonstrate that severe degradation phenomena may occur at the back polysilicon interface depending on the back-gate voltage during stress. The nature of these phenomena becomes evident when the back-gate bias is such that the back interface is coupled or decoupled from the front gate electrical characteristics.     

On the conduction mechanism in polycrystalline silicon thin-film transistors

Physical and electrical analyses were carried out on n-channel polycrystalline silicon thin-film transistors (nTFTs) with active regions as thin as approximately 6 nm. Such thin active regions extinguish the dominating effects of anomalous leakage and allow the conduction energy barrier height to be analyzed as a function of gate voltage in the femtoampere source/drain current regime. Grain size statistics were determined using plan view transmission electron microscopy. It is shown for the first time that in the absence of anomalous leakage, the barrier height does not decrease with decreasing gate voltage. In addition, the maximum measured barrier height is almost independent of active region thickness and grain size statistics. The source/drain current at low lateral field and high vertical field is also independent of channel length for all devices with length varied over an order of magnitude. These important discrepancies with existing TFT conduction theory are discussed within a physics-based model that addresses the effects of disorder-induced localized electron states in the bandgap. Besides describing existing data and well-known TFT behavioral trends, the model predicts a previously unknown relationship between threshold voltage variation, average threshold voltage and the number of grains in the channel. Analysis of data gathered from hundreds of devices of different dimensions across three different grain size distributions not only leads to agreement with the model but also to a remarkable universal behavior linking electrical and physical properties. This study shows the physics of polycrystalline silicon TFT conduction to be of the same form as amorphous and single crystal devices with the degree of disorder as the sliding scale between the two extremes.     

Air-gap polycrystalline silicon thin-film transistors for fully integrated sensors

Air gap thin-film transistors (TFTs) were fabricated using a solid phase crystallization process. Undoped polycrystalline silicon (polysilicon) was used as the active layer and a highly doped polysilicon bridge was used as the gate, which promotes the air gap. These TFTs have comparable threshold voltage (V/sub T/) and subthreshold slope characteristics to TFTs fabricated using pulsed laser crystallization, and using silicon dioxide as gate insulator. The low value of V/sub T/ is very important for low power consumption. Moreover, the air-gap TFT fabrication process is compatible with low-temperature glass substrate technology, which allows the integration of sensors and electronics circuits.     

Effects of gamma-ray irradiation on polycrystalline silicon thin-film transistors

The effects of gamma-ray irradiation on the performance of polycrystalline silicon thin-film transistors are investigated. After irradiation, the threshold voltage of the TFTs is shifted negatively and well-defined kinks are formed in the subthreshold regions of the transfer characteristics, explained by the turn-on of back channel and sidewall leakage current paths. In the non-irradiated device, the leakage current I_L is controlled by the reverse biased drain junction, while after irradiation I_L is limited by the intrinsic resistance of the polysilicon material itself.     

Dimensional effects on the reliability of polycrystalline silicon thin-film transistors

We found that for unpassivated short-channel TFTs, hot carrier stress-induced degradation phenomena are different with various channel geometries. For device with a wide channel width, the threshold voltage is increased while the subthreshold swing is almost unchanged. The stress-induced oxide-trapped charges are responsible for the degradation. For others with narrow channel widths after stress, on the contrary, the subthreshold swing and I_min are increased, the trap density is greatly increased and the trap-enhanced kink effect is also observed. This is due to the generation of stress-induced grain boundary traps near the drain side. Additionally, the stress-induced degradations of passivated TFTs with various geometries are identical. The increased defect density dominates the mechanism since the hot-carrier stress tends to break the passivated Si-H bonds.     

Hydrogenation of polycrystalline silicon thin film transistors byplasma ion implantation

Both n- and p-channel polycrystalline silicon (poly-Si) thin film transistors (TFT's) have been hydrogenated using the plasma ion implantation (PII) technique. Significant improvements in device characteristics have been obtained. Because PII is capable of greater dose rates than plasma immersion, it allows for significantly shorter process times than other methods investigated thus far     

Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors

Experimental investigation of the substrate current I_sub as a function of the gate voltage has been performed in n-channel polycrystalline silicon thin-film transistors (polysilicon TFTs), considering the drain voltage as a parameter of the study. At low gate voltages, I_sub exhibits a peak located close to the threshold voltage of the transistor due to hot-carriers generated by impact ionization. At higher gate voltages, I_sub increases monotonically with increasing the gate voltage, which is attributed to the temperature rise owing to self-heating. The degradation behavior of polysilicon TFTs, stressed under two different gate and drain bias conditions that cause the same substrate current due to hot-carrier and self-heating effects, is investigated.     

Emitter and base transit time of polycrystalline silicon emittercontact bipolar transistors

The author formulates transit time in the neutral emitter region, τ_E, and in the neutral base region τ_B, of polycrystalline silicon emitter contact bipolar transistors. An analytical theory derived for τ_E of polysilicon emitter contact bipolar transistors and its dependence on the emitter junction depth, the polysilicon thickness, and the base width are presented. The influence of bandgap narrowing on τ_E and τ_B is analyzed. Bandgap narrowing increases τ_E , but τ_B is insensitive to it. τ_E is proportional to base width W_B and τ_B to W²_B. τ_E is not negligible compared to τ_B when W_B is less than 100 nm. Reducing emitter junction depth and polysilicon thickness is indispensable to developing shallow base bipolar transistors     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

双栅无结晶体管阈值电压模型

无结晶体管是近年来纳米SOI MOS器件领域的研究热点,相对于传统晶体管具有明显的优势。本文针对全耗尽型无结晶体管,基于二维泊松方程,建立了电势分布解析模型。根据该模型可以得到阈值电压模型。利用建立的解析模型和半导体器件仿真软件MEDICI,探讨了栅压和器件结构参数对电势分布和阈值电压的影响。该模型简单且与仿真结果吻合良好。     

Electronic characterization of double-gate thin film transistors

A method of determining the electronic parameters, i.e. the free charge carrier density, the surface state density and the bulk trap state density, of the semiconductor in double-gate thin film transistors is described. The method is based on a comparison of the calculated field-effect conductance with the observed drain current of the device. The theory is formulated such that it applies even though the semiconductor is thin compared with the effective Debye lengths. An illustrative example of the method applied to a CdSe double-gate thin film transistor is given.     

Modeling of ultrathin double-gate nMOS/SOI transistors

An analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices. The model is based on Poisson's equation, containing both the doping impurity charges and the electron concentration. An original assumption of the constant difference between surface and mid-film potentials is successfully introduced. The model provides explicit expressions of the threshold voltage and threshold surface potential, which may no longer be assumed to be pinned at the limit of strong inversion, and demonstrates the nearly ideal subthreshold slope of ultrathin double-gate SOI transistors. Very good agreement with numerical simulations is observed. Throughout the paper we give an insight into weak inversion mechanisms occurring in thin double-gate structures     

Tunable contact resistance in double-gate organic field-effect transistors

A study of the contact resistance (R_sd) in pentacene-based double-gate transistors is presented. In top-contact transistors, as the negative bias of the additional top-gate bias is increased, R_sd decreases by over five orders of magnitude for small bottom-gate voltages. In bottom-contact transistors, R_sd is reduced by about ten times for all bias values, implying improved charge transport in all operating regimes. The different tunability of R_sd in top/bottom-contact transistors is attributed to different charge injection modulation by the coplanar/staggered top gate. Therefore, double-gate architecture offers a novel and effective approach to limit R_sd and its relevant impacts on organic transistor.     

High performance low temperature metal-induced unilaterallycrystallized polycrystalline silicon thin film transistors forsystem-on-panel applications

Thin film transistors (TFTs) with low-temperature processed metal-induced laterally crystallized (MILC) channels and self-aligned metal-induction crystallized (MIC) source and drain regions have been demonstrated recently as potential devices for realizing electronics on large-area, inexpensive glass panels. While these TFTs are better than their solid-phase crystallized counterparts in many device performance measures, they suffer from higher off-state leakage current and early drain breakdown. A new technology is proposed, employing metal-induced-unilateral crystallization (MIUC), which results in the removal from the edges of and within the channel region all major grain boundaries transverse to the drain current flow. Compared to the conventional “bilateral” MILC TFTs, the new MIUC devices are shown to have higher field-effect mobility, significantly reduced leakage current, better immunity to early drain breakdown, and much improved spatial uniformity of the device parameters. Thus they are particularly suitable for realizing low temperature CMOS systems on inexpensive glass panels     

Improving hydrogenation efficiency of polycrystalline silicon thin film transistors by a new approach

In this paper, a new hydrogenation process of poly-Si thin film for the fabrication of poly-Si thin film transistors (TFTs) is proposed. In the new approach, the hydrogenation of TFTs is performed before deposition of contact metal. N-channel and p-channel poly-Si TFTs with various channel lengths and widths were fabricated with the new and conventional processes for comparison. The results verified that the efficiency of hydrogenation has been improved remarkably by the new process. The field-effect mobility of carriers, the on state current, threshold voltage and the on/off states current ratio have been greatly improved, and the trap state density has been reduced significantly.     

Silicon-on-insulator approach for power IC's integrating verticalDMOS and polycrystalline silicon CMOS thin-film transistors

A novel approach for the monolithic integration of low-voltage logic and analog control circuits with vertical-current flow power transistors is described. This is achieved by fabricating a CMOS device family, using polycrystalline-silicon thin-film transistors (TFTs), on the field oxide of a single-crystal power device. Parasitic interactions between the control and power devices are eliminated in a simple, inexpensive, and easily manufacturable process. The technology is capable of supporting both MOS and bipolar power devices and the presence of the TFT circuits places no restriction on the maximum voltage or current of the power device. The TFTs exhibit good electrical characteristics and the power devices are not compromised by the addition of the TFT control circuits. This concept is demonstrated by the fabrication of a vertical DMOS power transistor with >100-V, >45-A capability, monolithically integrated with current-limiting and temperature-limiting functions     

Threshold-voltage variability analysis and modeling for junctionless double-gate transistors

This paper presents a detailed analysis on the variation sources in junctionless double-gate transistors using numerical device simulation. Comparison with conventional ultra-scaled devices is also included in the study. When channel thickness is reduced to 10 nm or below, thickness variation becomes a significant source of threshold voltage variation even though random dopant fluctuation has been considered the most significant one, especially in the highly doped junctionless channel. When accounting for volume inversion in the thin silicon film, we propose a modeling approach to estimate the film thickness variation impact on threshold voltage using effective film thickness. Our study suggests that when T_Si is less than 4 nm, the threshold voltage becomes less sensitive to film thickness variation, partly due to quantum confinement.     

关于短沟道双栅无结型晶体管的仿真研究

We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed.Distributions of electron concentration,electric field and potential in the body channel region are also analyzed.Comparisons with conventional inversion-mode(IM) FETs,which can demonstrate the advantages of JL FETs,have also been performed.