Regenerative feedback repeaters for programmable interconnections

The use of regenerative feedback repeaters to reduce the delay in programmable interconnections is described. A static, complementary regenerative feedback (CRF) repeater is proposed. This CRF repeater locally regenerates the new level for a fixed time after a transition has been detected. Design issues and limitations are discussed. It is shown that rising transitions can propagate faster than falling transitions through a chain of overdriven nMOS switches with CRF repeaters. Experimental results from a 1.2 μm CMOS implementation show that the loaded delay through 64 switches for static and dynamic repeaters can be reduced by a factor 1.4-2 over conventional repeaters     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion

Signal propagation delay on a multi-source multi-sink bidirectional bus has a dominant effect on high-performance chips. This work presents a novel greedy algorithm that minimizes the critical propagation delay of an RLC-based bus. Based on the topology of a multi-source multi-sink bus and the RLC delay model, the proposed algorithm inserts signal repeaters into the critical path of the RLC-based bus and adjusts their sizes to minimize the maximal propagation delay. This procedure is repeated until no additional improvement is needed. Several buses with various topologies are tested using the proposed algorithm in deep submicron technologies. Experimentally, the critical delay in an RLC-based bus can be reduced dramatically by up to 62.4% with inserted repeater sizes of 24 and execution time of 1.65 s on average. Moreover, average delay reduction, repeater sizes, and running time for 0.18 μm technology are 5.8%, 6.4%, and 26.2%, respectively, better than those of 0.35 μm. Additionally, the topologies of all of the RLC-based buses with inserted repeaters in deep submicron technologies are simulated using HSPICE. The error ratio in the critical delay of a bus with inserted repeaters determined by comparison with HSPICE is 2.7% on average. The proposed algorithm is simple and extremely practical.     

Automatic on-off switching repeater for DS/CDMA reverse linkcapacity improvement

We propose an automatic on-off switching (AOS) repeater that is switched off automatically when there is no active user within its coverage. With the AOS repeater, we can reduce the unnecessary noise enhancement. The reverse link capacity of a DS/CDMA system with AOS repeaters is analyzed mathematically and compared with that of a system with conventional repeaters. Also, the AOS circuit in a repeater can protect the reverse link capacity of a DS/CDMA system from excessive noise enhancement by abnormal repeaters. From the numerical results, noticeable improvement with the AOS repeaters is shown     

Differential current-sensing for on-chip interconnects

This paper presents a differential current-sensing technique as an alternative to existing circuit techniques for on-chip interconnects. Using a novel receiver circuit, it is shown that, delay-optimal current-sensing is a faster (20% on an average) option as compared to the delay-optimal repeater insertion technique for single-cycle wires. Delay benefit for current-sensing increases with an increase in wire width. Unlike repeaters, current-sensing does not require placement of buffers along the wire, and hence, eliminates any placement constraints. Inductive effects are negligible in differential current-sensing. Current-sensing also provides a tighter bound on delay with respect to process variations. However, current-sensing has some drawbacks. It is power inefficient due to the presence of static-power dissipation. Current-sensing is essentially a low-swing signaling technique, and hence, it is sensitive to full swing aggressor noise.     

Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects

In this paper, hybrids based on current-sensing and repeaters are proposed for on-chip interconnects in an effort to overcome the limitations of these techniques. A novel receiver for current-sensing results in static power savings and allows an easier transition from current-sensing to traditional full rail voltage signals. Measurements of hybrids on a 0.18-m CMOS technology show significant gains over repeater insertion in delay across wire lengths. Hybrids can also be used in placement constrained and low-noise scenarios to achieve delay and power benefits.     

Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion

Capacitive crosstalk between adjacent signal wires has significant effect on performance and delay uncertainty of point-to-point on-chip buses in deep submicrometer (DSM) VLSI technologies. We propose a hybrid polarity repeater insertion technique that combines inverting and non-inverting repeater insertion to achieve constant average effective coupling capacitance per wire transition for all possible switching patterns. Theoretical analysis shows the superiority of the proposed method in terms of performance and delay uncertainty compared to conventional and staggered repeater insertion methods. Simulations at the 90-nm node on semi-global METAL5 layer show around 25% reduction in worst case delay and around 86% delay uncertainty minimization compared to standard bus with optimal repeater configuration. The reduction in worst case capacitive coupling reduces peak energy which is a critical factor for thermal regulation and packaging. Isodelay comparisons with standard bus show that the proposed technique achieves considerable reduction in total buffers area, which in turn reduces average energy and peak current. Comparisons with staggered repeater which is one of the simplest and most effective crosstalk reduction techniques in the literature show that hybrid polarity repeater offers higher performance, less delay uncertainty, and reduced sensitivity to repeater placement variation.      

Noise and error rate performance of semiconductor laser amplifiers in PCM-IM optical transmission systems

Applications of semiconductor laser amplifiers in intensity modulated digital optical transmission systems were studied theoretically. An optical linear amplifier repeater between electronically regenerating terminal repeaters and an optical linear preamplifier in front of a photodetector in an electronically regenerating repeater are discussed. Both traveling-wave type and Fabry-Perot cavity type laser amplifiers are considered. The noise and error rate performance in these systems are evaluated using formulations for semiconductor laser amplifiers. The mean and variance in the optical amplifier output photons calculated by the photon master equation [1] is used to obtain the worst case variance in the equalized output voltage [2] for these systems. The required receiving power reduction from direct detection scheme by a preamplifier system and the repeater spacing expansion between two electronically regenerating terminals by an optical linear amplifier repeater system are delineated.     

A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment     

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion

/sup A/ new approach to handle inductance effects for multiple signal lines is presented. The worst-case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (L/sub eff/) for multiple lines. Based on a look-up table for L/sub eff/, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlists for multiple lines, this approach greatly improves the computational efficiency and maintains accuracy for timing and signal integrity analysis. We apply these models to repeater insertion in critical paths and find that, for a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC models.     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

A single-frequency communications system

In those radio communications applications where area coverage is not desired, a series of repeaters, each operating at low power, can be used to extend the radio over long distances. Microwave relay systems operate on this principle with each node representing a point of potential local distribution. Where it is desirable to have the nodes closely spaced, such as along a highway, it becomes desirable to utilize a single frequency for all transmissions in one direction in the interest of conserving spectrum. This paper covers such a system operating in the 935-MHz band. The system described provides both the "backbone" communications system which employs single-frequency repeaters and the "roadside" communications from the repeater node points to users in their vehicles. The functioning of the repeaters is described, and the relationship between signal levels, isolation, external noise levels, and thresholds is presented. Both analog and digital modulations are employed, and it is shown how each repeater is remotely switched between "backbone" and "roadside" communications modes. Extensions from current single-channel to multiple-channel operation is described in terms of the application to a variety of highway-related uses. The results of propagation experiments both along the "backbone" and on the "roadside" are described and related to theoretical models. From these data, conclusions can be drawn about the relationship between repeater spacing, height, and power level, as well as their relationship to user antenna height, output power, and receiver sensitivity.     

Optical Fiber Transmission System Demonstration Over 32 km with Repeaters Data Rate Transparent Up to 2.3 Mbits/s

An initial optical fiber transmission system under development for Army long haul tactical communications is described and evaluated. The system interfaces with the 2.304 Mbit/s data input and output of an Army inventory multiplexer and its orderwire. The system includes transmitter and receiver end terminals, three data rate transparent repeaters, 8 km of graded index optical fiber, plus three optical attenuators and various optical connectors for simulating transmission up to 32 km. Long repeater spacing is achieved using low loss fiber, semiconductor lasers stabilized using optical feedback, and avalanche photodiodes. The system met all of the specified requirements and shows that optical fiber transmission systems have excellent prospects of meeting full military specifications. The versatility of data rate transparent repeaters is achievable even for transmission up to the 64 km distance desired for Army long haul tactical communications.     

Design and characterization of a CMOS off-chip driver/receiver withreduced power-supply disturbance

A CMOS off-chip signal driver that achieves a 2.5-3 times smaller di/dt noise than the conventional design while not incurring the penalty of signal delay is described. It minimizes L di/dt effects by reducing the output signal swing by about a factor of 2 and by providing a controlled ramp rate for the output current. The circuit has a nearly constant output resistance for source termination of transmission lines, and includes a receiver designed for the smaller signal swing. Simulations show a driver-receiver delay of 3 ns for a 7.5-cm line on a multichip package with a peak di/dt of only 12 mA/ns. Driver-receiver delay and noise measurements are also presented     

Coding for system-on-chip networks: a unified framework

Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of tradeoffs between bus delay, codec latency, power, area, and reliability. Using simulation results in 0.13-/spl mu/m CMOS technology, we show that coding is a better alternative to repeater insertion for delay reduction as it reduces power dissipation at the same time. For a 10-mm 4-bit bus, we show that a bus employing the proposed codes achieves up to 2.17/spl times/ speed-up and 33% energy savings over a bus employing Hamming code. For a 10-mm 32-bit bus, we show that 1.7/spl times/ speed-up and 27% reduction in energy are achievable over an uncoded bus by employing low-swing signaling without any loss in reliability.     

一种基于目标延迟约束缓冲器插入的互连优化模型

基于分布式RLC传输线,提出在互连延迟满足目标延迟的条件下,利用拉格朗日函数改变插入缓冲器数目与尺寸来减小互连功耗和面积的优化模型. 在65nm CMOS工艺下,对两组不同类型的互连线进行计算比较,验证该模型在改善互连功耗与面积方面的优点. 此模型更适合全局互连线的优化,而且互连线越长,优化效果越明显,能够应用于纳米级SOC的计算机辅助设计和集成电路优化设计.     

Distributed space-time coding for multihop transmission in power line communication networks

In this paper, we consider transmission in relatively wide-stretched power line communication (PLC) networks, where repeaters are required to bridge the source-to-destination distance. In particular, it is assumed that each network node is a potential repeater and that multihop transmission is accomplished in an ad hoc fashion without the need for complex routing protocols. In such a scenario, due to the broadcasting nature of the power line channel, multiple repeater nodes may receive and retransmit the source message simultaneously. It is shown that, if no further signal processing is applied at the transmitter, simultaneous retransmission often deteriorates performance compared with single-node retransmission. We therefore advocate the application of distributed space-time block codes (DSTBCs) to the problem at hand. More specifically, we propose that each network node is assigned a unique signature sequence, which allows efficient combining at the receiver. Most notably, DSTBC-based retransmission does not require explicit collaboration among network nodes for multihop transmission and detection complexity is not increased compared with single-node retransmission. Numerical results for multihop transmission over PLC networks show that DSTBC-based retransmission achieves a considerably improved performance in terms of required transmit power and multihop delay compared with alternative retransmission strategies.     

Low-Noise Ultralinear Line Repeaters for the L5 Coaxial System

Two major characteristics of the coaxial cable that are of paramount importance in the design of coaxial line repeaters are the nominal cable loss and the variation in the cable loss due to seasonal variations in cable temperature. As a result, there are two types of line repeaters used to equalize for the cable loss characteristics. One is a low-noise ultralinear fixed-gain amplifier. It is designated the basic repeater and is used to equalize for the nominal loss of the coaxial cable. The second type, called the regulating repeater, includes a basic repeater plus additional circuitry which automatically corrects for dynamic variations in cable loss due to temperature. Some of the important design techniques that are used to achieve these low-noise ultralinear repeaters are described. In addition, an analysis of the steady-state response of a tandem string of regulating repeaters is included.     

Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints

Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7% as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect.