Low-power and high-performance techniques in global interconnect signaling

In this article, two accurate and efficient approaches are proposed to optimize the power and delay of global interconnects in VLSI ICs. We modify the conventional buffer insertion and low swing methods for delay and power optimization of various lengths of the global interconnects. As such, we address non-equidistance buffer insertion (NEBI) and current-mode driver and receiver (CMDR) techniques along with our smart optimization procedure. It is shown that the optimized low swing CMDR technique is efficient for global interconnects of the length equal or longer than 5 mm, and the improved buffer insertion technique, NEBI, is a perfect choice for the short global interconnects. Additionally, a random search algorithm known as simulated annealing (SA), improved by an intelligent method using a piecewise linear and exponential cost function, is employed for optimization of the power and delay. To this end, we have implemented a smart CAD tool that works interactively with HSPICE to achieve accurate and reliable design results. For verification purposes, several circuits are designed and simulated in 0.25, 0.18, and 0.13 μm CMOS technologies. The simulation results verify a significant reduction in the power and delay of global interconnects compared to other methods in the literature.     

Low-power encodings for global communication in CMOS VLSI

Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tristate on-chip buses with level or transition signaling     

Differential current-mode sensing for efficient on-chip global signaling

We present a new on-chip signaling method that relies on differential current-mode sensing to improve both delay and energy dissipation compared to conventional inverter repeaters. The proposed method can be used for point-to-point as well as N-to-1 connections. Several experimental point-to-point transceivers with different interconnect length and an inverter repeater-based interconnect were implemented in 0.11 /spl mu/m, 1.2V CMOS. Hardware measurements indicate that the proposed current-sensed transceiver produces 65% of the delay/mm of a repeater-based transceiver while dissipating 51% of its average switching energy/mm for a 10 mm interconnect. An additional 10% energy reduction relative to the inverter-repeater transceiver is possible if shorter current pulses are transmitted through the interconnect.     

基于低轨通信星座的全球导航增强系统

针对我国难以全球建站实现全球连续监测,以及当前全球卫星导航系统(GNSS)精密定位收敛速度慢的难题,提出一种基于低轨全球通信星座的全球导航增强系统。该系统不需独立建设,可与低轨通信星座融合发展。低轨卫星既可作为“天基监测站”,又可作为“导航信息源”。结合正在发展的低轨鸿雁全球通信系统进行仿真分析,作为“天基监测站”时,通过配置高精确度GNSS接收机,采用“地面区域监测网+天基全球监测网”的观测体制,实现中高轨导航卫星与低轨通信卫星的联合精密定轨与钟差确定;作为“导航信息源”时,可降低几何精确度因子(GDOP)值和缩短精密单点定位首次收敛时间,相比只利用北斗单系统,在收敛时间方面具有显著优势,收敛时间从30 min缩短到5 min以内。     

一种低功耗多谐振荡式电压频率转换器设计

提出一种新型的低功耗多谐振荡式电压频率转换器电路的设计,采用0.18μm CMOS工艺制程,拥有较大的输入电压范围,根据CSMC 0.18μm工艺参数,在Spectre上仿真。结果表明,该电路在0~1.6 V的输入电压下输出0~2.0 MHz的频率信号,灵敏度1.25 MHz/V,输出频率相对误差小于6.8%,电路的最大功耗0.23 m W。得到预期的设计结果。     

Low-power digital systems based on adiabatic-switching principles

Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. We describe the fundamental adiabatic amplifier circuit and analyze its performance. The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation. We show how combinational and sequential adiabatic-switching logic circuits may be constructed and describe the timing restrictions required for adiabatic operation. Small chip-building experiments have been performed to validate the techniques and to analyse the associated circuit overhead     

A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

This paper describes an adaptive bandwidth bus (ABB) architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode signaling. Attaining a maximum aggregate bandwidth of 16 Gb/s (i.e., 1 Gb/s per line) across lossy on-chip interconnects spanning 1.75 cm in length, the bus core fabricated in 0.35 /spl mu/m CMOS technology dissipates approximately 93 mW with a supply of 2.5 V and signal activity of 0.5, equivalent to 5.71 pJ/bit. Experimental results using a 16-bit reference bus design that can be externally programmed to operate in voltage, current or adaptive modes indicate a 50% reduction in power dissipation over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltage-mode (VM) sensing, respectively.     

Novel and robust silicon-controlled rectifier (SCR) based devices for on-chip ESD protection

Silicon-controlled rectifiers (SCRs) are frequently used to build on-chip electrostatic discharge (ESD) protection structures, but SCRs are not sufficiently robust to meet a wide range of ESD requirements in various integrated circuits. In this paper, a novel and robust SCR-based device called the HHLVTSCR is presented. It is demonstrated that HHLVTSCR can exhibit various characteristics useful for ESD solutions. An example is also included to illustrate how HHVLTSCRs can be used to provide ESD protection to a practical application.     

基于弱晶体管的低功耗XNOR门设计

XNOR门是构成Reed-Muller逻辑的基本门电路,现有的XNOR门电路由于信号摆幅的不完全性而导致后级亚阈功耗的存在.本文通过在信号非全摆幅的节点上增加弱晶体管来实现信号的全摆幅,达到消除亚阈功耗,实现低功耗设计的目的.所提出的方法应用于两个典型的XNOR门电路的改进设计中,经PSpice模拟,其功耗改进超过20%.进一步应用到全加器的设计中,结果也证实了此方法的有效性.     

Low-power pulsed hybrid flip-flop based on a C-element

This paper presents a new flip-flop design featuring implicit pulse-triggered structure in which a dynamic front-end stage and a static back-end one are adopted, thereby, it is considered as a hybrid flip-flop possessing both low-power and high-performance targets. Proposed flip-flop is implemented by a sampling circuit, a C-element for rise and fall paths, and a keeper stage. Simulation results in 45 nm CMOS technology with a 1 V supply voltage demonstrate that 27.8% and 16.9% reductions in terms of power consumption as compared to all other reported flip-flop designs in 25% and 50% data activities, respectively. Moreover, utilizing only four clocked transistors along with transition condition technique make proposed design fast and power-efficient in all activity factors, and exhibiting 5% enhancement in speed. Hence, other exploitable advantage of presented design is power-delay-product (PDP_DQ) index whose improvement ranges from 16.7% to 56%. It is also indicated that presented scheme having negative setup time near zero and considrable hold time contains only 17 transistors severely affecting layout area efficiency being by as much as 12%. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance in power dissipation and PDP_DQ metrics.     

Low-power log-MAP decoding based on reduced metric memory access

Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards such as W-CDMA and CDMA2000. Although several low-power techniques have been proposed, power consumption is still a major issue to be solved in practical implementations. Since turbo decoding is classified as a memory-intensive algorithm, reducing memory accesses is crucial to achieve a low power design. To reduce the number of memory accesses for maximum a posteriori (MAP) decoding, this paper proposes an approximate reverse calculation method that can be implemented with simple arithmetic operations such as addition and comparison. Simulation results show that the proposed method applied to the W-CDMA standard reduces the access rate of the backward metric memory by 87% without degrading error-correcting performance. A prototype log-MAP decoder based on the proposed reverse calculation achieves 29% power reduction compared to a conventional decoder that does not use the reverse calculation.     

UWB低功耗无线视频网络的构建

超宽带（UWB）通信技术与其它无线通信技术相比有很大区别,它具有低功耗、数据传输速率高、信号功率谱密度低、安全性高等优点．尤其适用于短距离便携设备的高速视频传输。本文介绍了UWB的技术要点．发展现状和应用于视频传输的优势．并构建了基于UWB技术的低功耗无线视频传输网络的基本模型。     

中红外片上集成光电子综述（特邀）

信息技术的发展使得通讯波段集成光子技术在过去的几十年中被广泛重视并取得了突出进展,目前已走向商业化,这一技术的发展也激发了人们对于中红外波段（2~20 μm）片上光子集成的兴趣。中红外波段在空间光通信、热成像、物质探测分析等关乎国家发展、国防安全、民生改善等技术领域具有重要的应用前景。利用半导体工艺实现中红外光电子系统芯片小型化在尺寸、功耗以及大规模量产部署具有重大优势。因此,发展中红外片上集成光电子技术具有重大意义。文中主要针对于中红外波段片上集成的一些关键基础器件（如:调制器、探测器）的突破性进展及代表性工作进行了回顾;对各器件的种类、性能、参数及加工手段分别进行了较为全面的调研与比较;同时,也对器件的发展进程、亟待解决的问题以及对未来的展望进行了总结。     

Low-power current-reused RF front-end based on optimized transformers topology

This paper discusses the design, analysis and performance of a 2.4 GHz fully integrated low-power current-reused receiver front-end implemented in 0.18 μm CMOS technology. The front-end is composed of a single-to-differential low-noise amplifier (LNA), using high-Q differential transformers and inductors and a coupled switching mixer stage. The mixer transconductor and LNA share the same DC current. Measurements of performance show a conversion gain of 28.5 dB, noise figure of 6.6 dB, 1 dB compression point of −32.8 dBm and IIP3 of −23.3 dBm at a 250 kHz intermediate frequency, while dissipating 1.45 mA from a 1.2 V supply.     

Low-power broadband quadrature signal generator based on phase-tunable dividers

This paper presents the design and experimental results of a low-power 300–960 MHz I/Q signal generator for low-IF receivers. The circuit is based on phase-tunable dividers and uses delay-locked loops, which provide phase accuracy for the quadrature signals as well as low-sensitivity of the phase error against temperature and power supply variations. Thanks to the adopted technique, the phase error can be further reduced by trimming the reference voltage of the delay-locked loops through a calibration digital word, which can be stored in a non-volatile memory during manufacturing. The I/Q generator exhibits an absolute phase error before calibration that is lower than 1.5°. The I/Q phase drift due to temperature variations from ?40 to 85 °C and power supply variations from 1.1 to 1.3 V is 0.3° and 0.2°, respectively. By dividing the overall frequency range into four 165-MHz wide sub-bands and using only four 5-bit calibration words, the I/Q phase variation with respect to frequency, temperature, and power supply is lower than 1° in the 300–960 MHz operating band. The I/Q generator is implemented in a 90-nm CMOS technology and exhibits a current consumption as low as 0.5 mA.     

Low-power fault-tolerant interconnect method based on LCDMA and duplication

High computing capabilities and limited number of input/output pins of modern integrated circuits require an efficient and reliable interconnection architecture. The proposed communication scheme allows a large number of IP cores to send data over a single wire using logic code division multiple access (LCDMA) technique. Reliability is increased by using hardware redundancy, and three LCDMA-based fault tolerant designs are proposed: (a) duplication with logic comparison (DLC), (b) conventional triple modular redundancy (TMR), and (c) triple modular redundancy with sign voter (TSV). With aim to detect a received bit from chip sequence, LCDMA–DLC and LCDMA–TSV designs compare absolute values of the sums, while LCDMA–TMR compares only sign bits of the sums generated at the outputs of decoders. All proposed designs are implemented in FPGA and ASIC technologies. MATLAB simulation results show that increasing the length of spreading codes affects to an increase in reliability. A comparative analysis of the proposed fault tolerant designs in terms of hardware complexity, latency, power consumption and error detecting and correcting capability is conducted. It is shown that LCDMA–DLC design has lower hardware overhead and power consumption, with satisfactory better bit error rate (BER) performance, in comparison to LCDMA–TMR and LCDMA–TSV approach.     

基于CPLD的低功耗爆炸场温度测试系统

为了测量爆炸场等恶劣环境下温度的动态变化,分析炸药或相关弹药的爆炸参数,设计了基于CPLD的低功耗温度存储式测试系统;运用钨铼热电偶温度传感器匹配先进的电源管理模块,并结合动态存储测试技术,能够应用于环境条件比较差的恶劣环境中,在可靠可信、微功耗的基础上能得到较好的实验数据。     

一种基于光学集成芯片的紧凑型结构光产生系统

过去的几十年中,结构光照明在三维立体成像和计算机视觉有着重要的应用。然而,传统结构光产生系统结构复杂、体积庞大,这严重限制了它的潜在应用价值。提出了一种用于产生结构光的紧凑型的光电集成芯片,这种芯片基于绝缘体上的硅（SOI）材料。该方法具有结构简单、输出稳定、设计灵活等优势。不同于传统的结构光发生系统,该方法中,光束的强度及相位调制以及光束间的相互干涉都是由片上系统操控的。这有效避免了外界扰动对光斑质量的影响,同时提升了系统的便携性。实现了全片上调控的红外结构光产生系统。该结构光芯片大小仅为0.5*0.5毫米,可以产生约200*200微米的结构光照明区域。芯片照明区域的大小和结构光的单元结构周期与光栅的结构设计和光源波长相关。此外,通过设计合理地设计芯片上的元件布局,我们可以得到多种不同结构的照明图样。     

Low-power analogue computational blocks based on high-performance floating-gate MOSFET resistor

This article proposes a new FGMOS-based programmable FGMOS resistor. A highly linear resistor is implemented by cancelling the non-term present in the drain current equation of MOSFET operating in the linear region. The inherited features of FGMOS resistor are simplicity, programmability, wider bandwidth and very low power dissipation without supply voltage. The power dissipation of the proposed FGMOS resistor is only 985 nW. Analogue computational blocks such as programmable reciprocal circuit, current to voltage converter and low-pass filter as applications of proposed programmable FGMOS resistor are also suggested. The power dissipation of reciprocal circuit and low-pass filter are 14.7 and 131 µW, respectively. To demonstrate the efficacy of the circuits, simulations are carried out using SPICE on 0.13 µm CMOS technology.