A decision-feedback equalizer with pattern-dependent feedback formagnetic recording channels

A new nonlinear equalizer for high-density magnetic recording channels is presented. It has a structure of the decision-feedback equalizer (DFE) with a nonlinear model at the feedback section and a dynamic threshold detector. The feedback nonlinear model is a sequence of look-up tables (LUTs) indexed by time, and each table is addressed by a transition pattern formed by one future and ν past transitions. We call this new nonlinear equalizer the pattern-dependent DFE (PDFE). The feedback nonlinear model cancels the trailing nonlinear intersymbol interference (ISI), and then the data decision is made by considering the precursor nonlinear ISI caused by one future symbol. We propose a tap optimization criterion SNR_d for the PDFE which in effect tries to maximize the output signal to noise ratio, and derive a closed-form solution for the tap values. We compare the detection performance of PDFE with that of the DFE and the RAM-DFE on experimental channels. The RAM-DFE is a DFE with one large LUT at its feedback section. The results show that the PDFE yields a significant performance improvement over the DFE and the RAM-DFE. Also the PDFE derived in this paper achieves a superior performance compared with the PDFE derived by the minimum mean-square-error criterion     

Pole-zero decision feedback equalization with a rapidly convergingadaptive IIR algorithm

A decision feedback equalizer (DFE) containing a feedback filter with both poles and zeros is proposed for high-speed digital communications over the subscriber loop. The feedback filter is composed of a relatively short FIR filter that cancels the initial part of the channel impulse response, which may contain rapid variations due to bridge taps, and a pole-zero, or IIR, filter that cancels the smoothly decaying tail of the impulse response. Modifications of an adaptive IIR algorithm, based on the Steiglitz-McBride (1965) identification scheme, are proposed to adapt the feedback filter. A measured subscriber loop impulse response is used to compare the performance of the adaptive pole-zero DFE, assuming a two-pole feedback filter, with a conventional DFE having the same number of coefficients. Results show that the pole-zero DFE offers a significant improvement in mean squared error relative to the conventional DFE. The speed convergence of the adaptive pole-zero DFE is comparable to that of the conventional DFE using the standard least mean square (LMS) adaptive algorithm     

A 35 Mb/s mixed-signal decision-feedback equalizer for disk drivesin 2-μm CMOS

A 35 Mb/s mixed-signal adaptive decision-feedback equalizer (DFE) has been implemented in a 2-μm CMOS technology. The DFE has four feedback taps for cancelling intersymbol interference (ISI) and one tap for cancelling dc offset. The ISI is cancelled using fully differential analog circuits. Coefficient adaptation is digital, and two adaptation rates are available. The DFE occupies 24 mm² and dissipates 165 mW     

Theoretical and Measured Performance of a DFE Modem on a Fading Multipath Channel

A decision-feedback equalizer (DFE) is the basis of a recent development of a quadruple diversity troposcatter modem which can operate up to a data rate of 12.6 Mbit/s in a 99% bandwidth of 15 MHz. In this paper a theoretical approach is developed for the calculation of average bit error rate (ABER), including the effects of intersymbol interference due to multipath and the finiteness of the transversal filters used to realize the DFE. By omitting the intersymbol interference effect, the calculation provides a lower bound which can be used to assess the intersymbol interference penalty for a particular DFE structure. The paper includes calculations of a DFE configuration which has a three tap forward filter with tap spacing equal to one-half a symbol interval. Measured performance results from fading channel simulator tests of a three tap forward filter DFE are presented for data rates from 1.5 to 12.6 Mbit/s and for a wide range of multipath statistical conditions. The results for this DFE configuration show (1) excellent agreement between calculated and measured ABER, (2) a small intersymbol interference penalty when the 2σ multipath spread is less than approximnately one-half the data symbol interval, and (3) successful operation at values of multipath spread up to twice the data symbol interval. In a sequel to this paper, the results of a field test of the DFE modem are presented. These live links test results are consistent with both the calculated and simulator measured data presented here.     

Complexity reduction and performance improvement of a decisionfeedback equalizer for 16QAM in land mobile communications

This paper proposes a complexity-reduced decision feedback equalizer (DFE) for 16-ary quadrature amplitude modulation (16QAM) using tap gain interpolation, bi-directional equalizing (BDE) and space diversity combining (SDC) to achieve high spectral efficiency and high quality data transmission over frequency-selective fading channels in land mobile communications. To reduce the amount of computation required for BDE and SDC, we propose a tap gain interpolation scheme and pre-decision schemes for both processes. Computer simulation of a (16QAM/TDMA system) confirms that the proposed scheme improves frequency-selective fading compensation performance by 6 dB or more while using only 27% of the computation of conventional single branch DFE receivers     

Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection

This paper presents an adaptive decision feedback equalizer (DFE) utilizing a hexagon eye-opening monitor to detect both the violation of the minimum eye and the severity of the violation so as to allow different step sizes to be used in search for optimal DFE tap coefficients. In addition, a new slope detection method is used to detect the deviation of received data symbols from the desired one so as to guide the direction of search for the optimal DFE tap coefficients. The proposed adaptive DFE allows designers to freely set DFE constraints such as the minimum vertical eye opening, the minimum horizontal eye opening, and the maximum jitter of the sampling clock so as to address the needs of different applications. To validate its effectiveness, the proposed adaptive DFE is embedded in a 2 Gbps serial link designed in an IBM 130 nm 1.2 V CMOS technology. The link is analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the proposed adaptive DFE is capable of opening completely closed data eyes at the far end of a 2-m FR4 channel with 75 % vertical eye opening, 78 % horizontal eye opening, and 21 % data jitter while consuming 17.38 mW.     

一个用于背板通信的24Gb/s高速自适应组合均衡器

本文介绍了应用于背板通信系统中均衡器的设计与实现.该均衡器采用连续时间线性均衡器（Continuous Time Linear Equalizer,CTLE）和2抽头判决反馈均衡器（Decision Feedback Equalizer,DFE）的组合结构来消除信道码间干扰中的前标分量和后标分量.在设计中,CTLE采用双路均衡器结构补偿信道不同频率的损耗,减小了电路的面积和功耗;DFE采用半速率预处理结构来缓解传统DFE结构中关键反馈路径的时序限制,并采用模拟最小均方（Least Mean Square,LMS）算法电路控制DFE系数的自适应.电路采用IBM 0.13μm BiCMOS工艺设计并实现,测试结果表明对于经过18英寸背板后眼图完全闭合的24Gb/s的信号,均衡后的眼图水平张开度达到了0.81UI.整个均衡器芯片包括焊盘在内的芯片面积为0.78×0.8mm²,在3.3V的电源电压下,功耗为624mW.     

An edge-based dual adaptive decision feedback equalizer for Gbps serial links

This paper presents an adaptive edge-DFE for 2PAM Gbps serial links. The optimal tap coefficients of the DFE are obtained by minimizing the jitter of received data. Reference voltage for generating DFE error signal is also obtained iteratively using an edge-DFE like algorithm. Issues critical to the proposed adaptive edge-DFE are examined in detail. The effectiveness of the proposed adaptive edge-DFE has been validated using a 5 Gbps serial link designed in a 65 nm 1.2 V CMOS technology. The effect of PVT (process, voltage, and temperature) variations on the performance of the proposed DFE has also been investigated. Simulation results demonstrate that the DFE is capable of opening completely closed data eyes when the DFE is absent. Equalized data have 55 % vertical-opening and 86.5 % horizontal eye-opening with 25 ns adaption time.     

Novel Techniques to Minimize the Error Propagation of Decision Feedback Equalizer in 8VSB DTV System

In this paper, novel and yet simple techniques are presented to minimize the error propagation caused by the large precursors and postcursors of the decision feedback equalizer (DFE) in 8VSB DTV system. A technique that selects a reference tap (symbol timing of DFE) from an estimated channel impulse response (CIR) is presented to minimize the effect of the large precursors. Another technique that selects the reference tap position, i.e., decision delay in a feedforward filter (FFF), from the estimated CIR and the amplitude of the selected reference tap is proposed to minimize the effect of large postcursors. The combined structure of a feedback filter (FBF) and Viterbi decoder for use in 8VSB DTV system is also proposed to replace the past unreliable decision symbols in FBF as well as to reduce the decision error probability. Simulation results show that our proposed DFE can prevent effectively the error propagation, in particular, by changing the reference tap and its position in FFF according to the channel condition. It is also shown that an echo removing capability of the proposed DFE, where 400 and 620taps are used for the FFF and FBF, respectively, is greater than that of conventional DFEs by about -20 mus in the single pre-echo of -10 dB channel and by about 10 mus in the single post-echo of -1 dB channel     

A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter

A 4-bit 6-GS/s pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-/spl mu/m CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each pipeline stage; hence the effective feedback delay requirement is relaxed by 6/spl times/. Code-overlapping of the 1.5-bit pipeline stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with /spl plusmn/0.25 LSB and /spl plusmn/0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8/spl times/1.6 mm/sup 2/ chip consumes 780 mW of power from a 1.8-V power supply.     

应用于10 Gbit/s光通信及背板传输的自适应均衡器设计

描述了一种既可用于背板传输也可用于光纤通信的高速串行收发器前端均衡器的设计。为适应光信号在传播中的色散效应,使用前馈均衡器(FFE)加判决反馈均衡器(DFE)的组合,取代了背板通信中常用的连续时间线性均衡器(CTLE)和DFE的组合。设计使用3 pre-tap、3 post-tap和1个main tap的抽头组合方式,兼顾pre-cursor和post-cursor的信号失真,有效补偿范围为15 dB。补偿系数采用完全自适应算法调整,对FFE采用模拟MSE算法调整,DFE引擎采用1/16速率数字sign-sign最小均方差(LMS)算法实现。芯片使用UMC 28 nm工艺流片,输入信号频率为10 Gbit/s。     

Tight Bounds on the Error Probabilities of Decision Feedback Equalizers

A decision feedback equalizer (DFE) with correct tap weights operating on a noisy channel is considered. We show how the results concerning a noiseless channel can be extended to yield tight bounds on the stationary error probability performance for the noisy case. The effect of noise on DFE performance is classified according to the noise distribution and the channel parameters.     

A CMOS adaptive continuous-time forward equalizer, LPF, and RAM-DFEfor magnetic recording

A continuous-time forward equalizer with one adaptive zero and a seventh-order linear-phase low-pass filter are described. The forward equalizer cancels precursor intersymbol interference (ISI). A mixed-signal four-tap RAM decision-feedback equalizer (DFE) is also included on the prototype to cancel the postcursor ISI. Both precursor and postcursor ISI are canceled in the analog domain. The adaption is done digitally. The low-pass filter and forward equalizer together occupy 6.7 mm² in a 1 μm CMOS process. They dissipate 280 mW from a 5 V supply when operating at 80 Mb/s. Including the RAM-DFE, the entire chip occupies 11.2 mm² and dissipates 630 mW     

Optimized decision-feedback equalization for convolutional coding with reduced delay

Error propagation is a significant problem with the decision-feedback equalizer (DFE) at low-to-moderate signal-to-noise ratios. In particular, when a DFE is concatenated with a convolutional code, the burst errors associated with error propagation can severely degrade performance, since the convolutional code is optimized for the additive white Gaussian noise channel. In this paper, we explore the compensation of error propagation in the DFE so as to break up error bursts and improve performance with convolutional codes, without incurring larger overall decoding delay. We propose certain stationary error models and derive a modified DFE (MDFE) based on these models which can compensate for the error propagation. The MDFE differs from the conventional DFE only in its tap values. The incorporation of the bias into the model and the removal of the bias during the design process is discussed. Simulations explore the performance of the MDFE for both uncoded and convolutionally coded systems. With coding, the MDFE can significantly improve on the conventional DFE in terms of bit-error rate, and the MDFE without interleaving can improve on the conventional DFE with interleaving in terms of decision delay.     

Performance of a hybrid decision feedback equalizer structure forCAP-based DSL systems

We study the performance of a class of derision feedback equalizer (DFE) structures for high-speed digital transmission systems. We first present mathematical formulation of minimum mean-square error (MMSE) and the optimum tap coefficients for various finite-length phase-splitting equalizers over the loop in the presence of colored noise, such as near-end crosstalk (NEXT) and far-end crosstalk (FEXT). The performance of the equalizers is also analyzed in the presence of narrowband interference and the channel reflections introduced by bridged taps. The hybrid-type DFE (H-DFE) is presented as a practical equalizer structure for these applications. The results of analysis show that the H-DFE has advantages in the performance and/or in the implementation complexity as compared with the existing DFE structures. An additional advantage of the H-DFE is in the transmission systems that employ the precoding technique. The precoding for the H-DFE allows the system to track small changes in the channel     

A robust adaptive DFE receiver for DS-CDMA systems under multipathfading channels

This paper presents a novel receiver design from signal processing viewpoint for direct-sequence code-division multiple access (DS-CDMA) systems under multipath fading channels. A robust adaptive decision-feedback equalizer (DFE) is developed by using optimal filtering technique via minimizing the mean-square error (MSE). The multipath fading channels are modeled as tapped-delay-line filters, and the tap coefficients are described as Rayleigh distributions in order to imitate the frequency-selective fading channel. Then, a robust Kalman filtering algorithm is used to estimate the channel responses for the adaptation of the proposed DFE receiver under the situation of partially known channel statistics. The feedforward and feedback filters are designed by using not only the estimated channel responses but the uncertainties and error covariance of channel estimation as well. As shown in the computer simulations, the proposed adaptive DFE receiver is robust against the estimation errors and modeling dynamics of the channels. Hence, it is very suitable for receiver design in data transmissions through multipath fading channels encountered in most wireless communication systems     

Joint coding and decision feedback equalization for broadbandwireless channels

This paper introduces a new approach for joint convolutional coding and decision feedback equalization (DPE). To minimize error propagation, the DFE uses a combination of soft decisions and delayed tentative decisions to cancel intersymbol interference (ISI). Soft decisions are obtained by passing the DFE output through a (soft) nonlinear device. This simple method is shown to perform almost as well as an optimum soft feedback approach on wireless channels with diversity. Tentative decisions from the Viterbi decoder are used to cancel ISI due to multipath with large delays, thus remedying the increasing effect of error propagation in channels with large delay spreads. We consider the use of this soft/delayed feedback DFE (S/D-DFE) technique in broadband wireless channels (with delay spreads up to several tens of the symbol period) typical in high-bitrate mobile data applications. Simulation results indicate that the proposed joint coding and S/D-DFE technique performs to within 1-2 dB [in required signal-to-noise ratio (SNR)] of an ideal coded DFE without error propagation. When combined with antenna diversity and a reduced-complexity DFE concept with adaptive feedforward tap assignment, it provides high packet throughput against Rayleigh fading, severe delay spreads, and high Doppler rates     

Tap-selectable decision-feedback equalization

This paper presents an adaptive tap assignment technique for improving the performance of a previously reported reduced-complexity decision-feedback equalizer (DFE) for broadband band wireless systems. The spacings of individual feedforward taps of the DFE are made selectable so that, when the channel consists of a sparsely distributed multipath with a large delay spread (e.g. “hilly terrain” (HT) delay profiles), the equalizer span can be increased without increasing the total number of taps. We propose simple tap selection algorithms and show that they provide: (1) performance gains over a contiguous-tap approach in various outdoor delay profiles and (2) improved robustness against fast fading     

A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization

A 5-bit 4.8 GS/s 4-way time-interleaved ADC is designed for a receiver front-end in a 0.13 $muhbox{m}$ CMOS technology. Each time-interleaved ADC uses look-ahead pipelined stages to enable higher sample rates and more linear residue characteristics than a conventional pipeline ADC. At 1.2 GHz per path, the residue amplifiers settle to 75% of their final value, however, the linear residue characteristics allows using digital reference calibration to enable 30.4 dB of SNDR with a 1.2 MHz input signal. A capacitor pre-charging technique reduces the memory effect errors of the incompletely settled residue to 2% of the stage output swing. The peak INL and DNL are measured as 0.65LSB and 0.55LSB, respectively. The measured ERBW is ${sim},$ 6.1 GHz. The ADC, including the reference buffers, consumes 300 mW from a 1.2-V supply while operating at 4.8 GHz conversion rate. A stage-by-stage feedback compensates the possible bandwidth limitation of the system using a per-stage speculative DFE. The DFE tap is adjustable between 0 and 0.4 using 8 control bits.      

A decision feedback equalizer with time-reversal structure

This work describes the use of a receiver with a time-reversal structure for low-complexity decision feedback equalization of slowly fading dispersive indoor radio channels. Time-reversal is done by storing each block of received signal samples in a buffer and reversing the sequential order of the signal samples in time prior to equalization. As a result, the equivalent channel impulse response as seen by the equalizer is a time-reverse of the actual channel impulse response. Selective time-reversal operation, therefore, allows a decision feedback equalizer (DFE) with a small number of forward filter taps to perform equally well for both minimum-phase and maximum-phase channel characteristics. The author evaluates the theoretical performance bounds for such a receiver and quantifies the possible performance improvement for discrete multipath channels with Rayleigh fading statistics. Two extreme cases of DFE examples are considered: an infinite-length DFE; and a DFE with a single forward filter tap. Optimum burst and symbol timing recovery is addressed and several practical schemes are suggested. Simulation results are presented. The combined use of equalization and diversity reception is considered