Formation of TiSi2 and shallow junction byAs+ ion-beam mixing and infrared rapid heat treatment

A technique for forming shallow junctions with low-resistance silicide contacts developed for the use in VLSI with scaled MOSFETs is discussed. The salicide (self-aligned silicide) MOSFET gate and source-drain features self-aligned refractory metal silicide and are isolated from one another even without any insulating spacer on the gate sides. A critical step in such a MOSFET fabrication process is the ion implantation through metal silicidation technique, which includes As⁺ ion-beam-induced titanium-silicon interface mixing and infrared rapid heat treatment to form simultaneously the n⁺-p junction and a high-quality TiN covered TiSi₂ contact layer     

Al/W/TiNx/TiSiy/Si barrier technology for1.0-μm contacts

A reliable contact diffusion barrier has been successfully formed by sintering in nitrogen a physically sputtered W/Ti bilayer. After a 650°C furnace anneal, a TiN_x/TiSi_y layer on contact with the silicon substrate was formed beneath the overlying W. No reaction between N₂ and W was observed. Arsenic implanted in the silicon substrate tended to retard the silicidation of titanium. Substantial redistribution of both B and As across the silicide layer was also observed during the contact sintering process. The 1.0-μ contacts fabricated with the Al/W/TiN_x/TiSi_y/Si barrier technology exhibited low and tightly distributed contact resistivities (less than 10^-6 Ω-cm²). No excessive leakage of the shallow junctions was observed even after thermally stressing the sample at 400°C for 8 h     

Various effects of silicidation on shallow p+ junctionsformed by BF2+ implantation into thin poly-Sifilms on Si substrates

Various effects of silicidation on shallow p⁺ n junctions formed by the scheme that implants BF₂⁺ ions into thin poly-Si films on Si substrates are described. A post-Ni silicidation just slightly improves the preformed junctions of the annealed sample. However, as the sample is first deposited with thin Ni films after the implantation and then annealed, the resulting junctions are much better than the preformed ones. Moreover, as the sample is deposited with Ti films, the resultant junctions are just slightly better the preformed ones     

Impact of Ge implantation on the electrical characteristics of TiSi2 p+/n shallow junctions with an a-Si (or apoly-Si) buffer layer

A new technology for forming a titanium-silicide shallow junction by combining germanium implantation with an amorphous-silicon (or a poly-silicon) buffer layer has been proposed for MOSFETs. The use of a buffer layer between Ti and Si can avoid the consumption of bulk-silicon and the recession of TiSi₂ film into the source/drain junctions during the silicidation process. In this study, the important role of germanium-implantation on the formation of TiSi₂ contacted p⁺/n junctions was examined. After subsequent implantation of Ge⁺ and B⁺ into the TiSi₂ film, samples were annealed at different temperatures to form p ⁺/n junctions and C54-TiSi₂. Since the penetration of titanium atoms was suppressed due to the germanium-implantation, the periphery leakage and the generation leakage were improved and TiSi₂/Si interfaces were even smooth. Therefore, p⁺/n junctions with a very low leakage current (0.192 nA/cm ² at -5 V) and an excellent forward ideality factor (n≈1.002) can be obtained. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth is 400     

Characteristics of sub-100-nm p+/n junctions fabricatedby plasma immersion ion implantation

Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p⁺/n diodes with junction depths below 100 nm. SiF₄ is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF₃ is implanted. Ultrashallow p⁺/n junctions are formed by annealing at 1060 °C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm ² in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 μs     

Technology limitations for N+/P+ polycidegate CMOS due to lateral dopant diffusion in silicide/polysilicon layers

The device degradation of dual-polycide-gate N⁺/P⁺ CMOS polycide transistors due to the lateral diffusion of dopants in the silicides is studied using a coupled 2-D process and device simulator. Design rule spacings between the NMOS and the PMOS transistor are given for various NMOS:PMOS gate area ratios and thermal processing conditions. The simulations show that contrary to previous findings, micrometer and submicrometer spacings are possible for certain silicide technologies using low-temperature or short higher-temperature furnace steps. Simulations show that CoSi₂ and TiSi₂ appear to be better candidates for submicrometer dual-gate applications than WSi₂     

Formation kinetics and structure of Pd2Si films on Si

Backscattering and X-ray techniques have been used to study properties of palladium silicide (Pd₂Si) formed by evaporating thin Pd layers on Si followed by heat treatment. The rate of formation of Pd₂Si in the temperature range of 200–275°C has been measured by 2-MeV ⁴He⁺ ion backscattering. The Pd₂Si layer is found to grow at a rate proportional to the square root of time for thicknesses ranging from approximately 200–4000 Å. The rate of growth is found to be independent of Si substrate orientation or doping type and the rate constant is found to fit a single activation energy of E_a = 1·5±0·1 eV over the temperature range measured. X-ray diffraction indicates the structure to be Pd₂Si with the basal plane roughly parallel to the substrate surface for films formed on 111, 110, 100 and evaporated (amorphous) silicon substrates. The degree of preferred orientation is markedly stronger on [111] Si. Ion channeling measurements confirm that in this case the c-direction of the Pd₂Si is parallel with the [111] direction in the underlying Si.     

Suppression of cobalt silicide agglomeration using nitrogen(N2+) implantation

In this paper, the effects of nitrogen coimplantation with boron into p⁺-poly gate in PMOSFETs on the agglomeration effects of CoSi₂ are studied. The thermal stability of CoSi₂/poly-Si stacked layers can be significantly improved by using nitrogen implantation. Samples with 40-nm cobalt silicide (CoSi ₂) on 210-nm poly-Si implanted by 2×10¹⁵/cm ² N₂⁺ are thermally stable above 950°C for 30 s in N₂ ambient. If the dose of nitrogen is increased up to 6×10¹⁵/cm², the sheet resistance of CoSi₂ film is not increased at all, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed     

Infrared cross-section measurements for crystals doped withEr3+, Tm3+, and Ho3+

The absorption and emission cross sections of the transition between the ground spin-orbit multiplet and the lowest excited multiplet were measured for Er³⁺, Tm³⁺, and Ho³⁺ ions in a variety of crystalline hosts. The materials that were investigated include LiYF₄, BaY₂F₈, Y ₃Al₅O₁₂, LaF₃, KCaF₃ , YAlO₃, and La₂Be₂O₅. The absolute magnitudes of the emission cross sections were determined from the absorption spectra, with the aid of the principle of reciprocity. The calculated radiative emission lifetimes derived from these measured cross sections agree well with the measured emission decay times for most materials. The potential use of these rare-earth-doped materials in pulsed laser applications requires that the ground state exhibit adequate splitting to minimize the detrimental effects of the ground state thermal population, and also that the emission cross section be sufficiently large to permit efficient extraction energy. The systems based on Ho³⁺ in the eightfold coordinated sites of LiYF₄, BaY₂F₈, and Y₃Al₅O₁₂ appear to be the most promising     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

Effect of i-layer parameters on the performance of Sin+-i-n+ homojunction far-infrared detectors

A unified formalism, including space-charge-limited (SCL) conduction, tunneling, and the multiple-image-force effect, is developed to perform a complete analysis of Si n⁺-i-n⁺ homojunction interfacial workfunction internal photoemission (HIWIP) FIR detectors. It is shown that due to the space-charge effect, the detector performance, such as cutoff wavelength (λ_c), quantum efficiency (η), dark current (I_d), noise equivalent power (NEP), etc., is strongly influenced by the i-layer thickness (W_i ) and compensating acceptor concentration (N_ai) in addition to the emitter layer parameters. As a result, the optimum operating conditions of detectors also depend on W and N_ai. The background limited performance (BLIP) is evaluated, and a critical W _i value is found for BLIP operation     

Gain measurement and upconversion analysis in Tm3+, Ho3+ co-doped alumino-zirco-fluoride glass

The small signal gain coefficients were measured in Tm³⁺,Ho³⁺ co-doped alumino-zirco-fluoride glass. A gain of 15%/cm at 2.05 μm was obtained for pump power density of 42 kW/cm². The temperature increase of the glass was found to be more than 150 K with this pump power, which was estimated from a comparison between fluorescence intensities of Tm^{3+ 3} F₄-³H₆ and Ho^{3+ 5} I₇-⁵I₈. An upconversion rate constant of 12.5×10^-17 cm³ sec^-1 from a coupled (Tm^{3+ 3}F₄, Ho^{3+ 5}I₇) level to a coupled (Tm^{3+ 3}H₅, Ho^{3+ 5}I₆) level was determined by fitting the experimentally obtained gain coefficients to the calculated one which takes into consideration any temperature increase     

Analytical models for n+-p+ double-gate SOIMOSFET's

Previously, we proposed n⁺-p⁺ double-gate SOI MOSFET's, which have n⁺ polysilicon for the back gate and p⁺ polysilicon for the front gate to enable adjustment of the threshold voltage, and demonstrated high speed operation. In this paper, we establish analytical models for this device, This transistor has two threshold voltages related to n⁺ and p⁺ polysilicon gates: V_th1 and V_th2, respectively. V _th1 is a function of the gate oxide thickness t_Ox and SOI thickness t_Si and is about 0.25 V when t_Ox/t_Si=5, while V_th2 is insensitive to t_Ox and t_Si and is about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing gate length. We show numerically that we can design sub 0.1 μm gate length devices with an an appropriate threshold voltage and an ideal subthreshold swing     

Structural, electrical and optical characterization of semiconducting Ru2Si3

Recent band structure calculations indicate, that ruthenium silicide (Ru₂Si₃) is semiconducting with a direct band gap. Electrical measurements lead to a band gap around 0.8 eV which is technologically important for fiber communications. This makes Ru₂Si₃ a promising candidate for silicon-based optical devices, namely LEDs. We present results on the epitaxial growth of ruthenium silicide films on Si(100) and Si(111) fabricated by the template method, a special molecular beam epitaxy technique. We structurally characterized the films by Rutherford backscattering and ion channeling, X-ray diffraction and transmission electron microscopy. To determine the electrical resistivity at high temperatures films were grown on insulating substrates to prevent parallel conduction through the substrate. Finally we show first results of the optical absorption performed by photothermal deflection spectroscopy indicating pronounced absorption above 1.5 eV.     

Laser action from Ho3+, Er3+, and Tm3+in YAlO3

Laser action has been observed for the following rare-earth ions in YAlO3:Ho³⁺(sensitized with Er³⁺and Tm³⁺), Er³⁺, and Tm³⁺(sensitized with Er³⁺) at wavelengths of 2.123, 0.851, and 1.861 μm, respectively. Measurements of spectroscopic properties, fluorescence kinetics, and laser performance of these ions in YAlO3are reported.     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

Thickness scaling issues of Ni silicide

Ni silicidation processes without a capping layer and with a TiN capping layer are studied from the point of view of process window, morphology of the resulting silicide, and mechanisms of degradation at higher temperatures. The thermal stability of NiSi films on As- and on B-doped (100) Si substrates was investigated for Ni film thicknesses ranging from 5 to 30 nm. While agglomeration was the mechanism of degradation for the thin films, both morphological changes and transformation to NiSi₂ were possible for thicker films depending on anneal temperature and time. Activation energy of 2.5 eV for NiSi on n+ (100) Si and p+ (100) Si was determined for the process of morphological degradation. The measured temperature and time dependences for the thermal degradation of NiSi films suggest that the activation energy for transformation to NiSi₂ is higher than for morphological degradation.     

Elevated n+/p junctions by implant into CoSi2formed on selective epitaxy for deep submicron MOSFETs

Very shallow elevated n⁺/p junctions formed by arsenic implant into or through cobalt silicide (CoSi₂) formed on selective epitaxial layers and their application to deep submicron n-channel MOSFETs were studied for the first time. PREDICT 1.6 simulation program was employed to choose the desired implant energies and annealing thermal cycle based on theoretically predicted silicide thickness. The implanted CoSi₂ elevated junctions had low reverse current and no bias voltage dependence up to 5 V. Diffusion current dominated the junction forward current, and good ideality factors close to 1 were obtained. A nearly abrupt junction doping profile was achieved. Deep submicron n-channel MOSFETs incorporating implanted CoSi₂ elevated junctions were demonstrated. Sharp turn-off and reasonably large drain currents were achieved     

A novel method for a smooth interface at poly-SiOx/SiO2 by employing selective etching

We have investigated the excimer laser recrystallization of slightly oxygen-added amorphous silicon (a-SiO_x) films for the application to the active layer of thin film transistors. We also propose a new method to reduce the surface roughness of poly-SiO_x films by etching the grain boundaries selectively. SEM images show that the Si-O bonds are well segregated into the poly-Si grain boundaries after laser crystallization and the surface morphology is remarkably improved after the selective buffered oxide etchant (BOE) etching of the grain boundaries. The electrical conductivity measurement shows that the activation energies of poly-SiO_x and poly-Si films have an identical value of 0.52 eV. This may confirm that oxygen-induced defects do not cause any difference in the electrical performance even at the oxygen concentration of 0.18 at.%. Moreover, the electrical mobility and subthreshold slope of poly-SiO_x TFTs are considerably improved by employing the proposed method, which smooths the poly-SiO_x/SiO₂ interface     

Stable gallium arsenide MIS capacitors and MIS field effecttransistors by (NH4)2Sx treatment andhydrogenation using plasma deposited silicon nitride gate insulator

The beneficial effects of sulfur passivation of gallium arsenide (GaAs) surface by (NH₄)₂S_x chemical treatment and by hydrogenation of the insulator-GaAs interface using the plasma-enhanced chemical vapor-deposited (PECVD) silicon nitride gate dielectric film as the source of hydrogen are illustrated by fabricating Al/PECVD silicon nitride/n-GaAs MIS capacitors and metal insulator semiconductor field effect transistors (MISFET). Post metallization annealing (PMA) at temperatures in the range 450-550°C is shown to be the key process for achieving midgap interface state density below 10 ¹¹/cm²/eV and maximum incremental transconductance, which is about 75% of the theoretical maximum limit. MIS capacitors are fabricated on (NH₄)₂S_x treated GaAs substrate using gate dielectrics such as PECVD SiO ₂ and silicon oxynitride to demonstrate that the PMA is less effective with these dielectrics because of their lower hydrogen content. The small signal AC transconductance, g_ms measurements on MISFETs fabricated using silicon nitride, have shown that the low-frequency degradation of g_ms is almost absent in the devices fabricated on (NH₄)₂S_x-treated GaAs substrates and subjected to PMA. The drain current stability in these devices is demonstrated to be excellent, with an initial drift of only 2% of the starting value. The dual role of silicon nitride layer, namely, protection against loss of sulfur and an excellent source of hydrogen for additional surface passivation along with sulfur is demonstrated by comparing the transconductance of MISFETs fabricated on GaAs substrates annealed without the nitride cap after the (NH₄)₂S _x treatment