Switched-capacitor integrators with low finite-gain sensitivity

Compensated SC integrator stages are analysed and compared with respect to their sensitivities to finite amplifier gain effects. Simple single-stage amplifiers may be used in such circuits even in highly selective filtering applications. This may allow an extension of the present frequency range of SC circuits.     

Switched-capacitor filters driven with very low voltage clock signals

It is well known that the switches of a very low voltage (1.5V) switched-capacitor filter in a standard CMOS process must be driven with a clock signal higher than the power supply, often generated on-chip. The authors present, however, a technique to implement very low voltage switched-capacitor filters with switches driven at the same very low voltages.<>     

Switched-capacitor track-and-hold amplifier with low sensitivity to op-amp imperfections

This paper describes a high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stage. It uses a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS THAs, the circuit does not need a sample-and-held input signal for its operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THA with earlier circuits utilizing CDS. The results verify that its operation is far more robust than that of any previously described THA.     

Switched-capacitor gain stage with reduced sensitivity to finite amplifier gain and offset voltage

A new switched-capacitor gain stage is presented that exhibits reduced sensitivity to operational amplifier gain and offset voltage. In addition, the design employs fewer switches and capacitors than previous techniques, and is less sensitive to parasitic capacitance effects. It should find wide application in A/D, D/A and other analogue arithmetic building blocks.     

基于MOCCCII-C的双二阶电流模式滤波器

本文提出了一种基于多输出端电流控制电流传输器(multiple outputs current controlled conveyors II)的双二阶电流模式滤波器电路,该滤波器结构简单,仅包含2个有源器件、2个接地电容.在不改变内部电路的情况下只需改变外部输入电流的接入方式和接入数目就可以实现二阶低通、高通、带通、带阻、全通滤波功能,面向实际电路完成了PSpice仿真,结果表明提出的电路正确有效.     

Adequate SC model of op-amp with finite DC gain and bandwidth suitable for two-op-amp SC biquad analysis

An adequate model of a nonideal op-amp operating in a two-op-amp SC biquad is derived. The model leads to an equivalent SC circuit containing ideal components. Substitution of any op-amp in an SC biquad by its equivalent SC circuit allows the exact frequency response of the biquad to be found easily, taking into account the finite DC gain and bandwidth of op-amps.     

Switched-capacitor DAC with analogue mismatch correction

A background calibration method for enhancing the accuracy and linearity of a switched-capacitor digital-to-analogue converter is described. The method can be used alone or in combination with mismatch shaping to achieve very high accuracy and linearity combined with high speed     

Switched-capacitor decimation filter design using time-multiplexing and polyphase decomposition of transfer functions with low denominator orders

A new switched-capacitor decimation filter design technique is presented. Based on a combination of the polyphase decomposition of IIR low-pass transfer functions having small denominator order and time-multiplexed operational transconductance amplifiers, the filter presents very low sensitivity to transfer function coefficients. It suits analog front-end systems by providing signal conditioning and relaxing the filtering requirements in converting between continuous-time and discrete-time signals. A prototype decimation filter has been designed and fabricated in a standard CMOS process to verify the proposed approach. In fully differential design, the filter has a die area of 2.8 mm², dissipates 67.2 mW out of a 5 V power supply and achieves a dynamic range of 58 dB at 1% THD. Experimental measurements are found in close agreement with theory.     

Design of a new low power MISO multi-mode universal biquad OTA-C filter

ABSTRACT

In this article, a new low-power multiple-input, single-output (MISO) multi-mode universal biquad operational transconductance amplifier-capacitor (OTA-C) filter with a minimum number of active and passive components is proposed. The proposed filter employs three OTAs, one inverter and two grounded capacitors. The proposed filter can realise all filter frequency responses including low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) in all operation modes including voltage, current, tranasresistance and transconductance modes using the same topology. Furthermore, sensitivity analysis is done which shows that the proposed filter has a low sensitivity to the values of the active and passive elements. The proposed filter is simulated in HSPICE using 0.18 µm CMOS technology. The HSPICE simulation results demonstrate that the proposed filter consumes only 35 μW at 2.5 MHz from a ±0.5 V supply voltage, while all of the transistors are biased in strong inversion region. Also, the simulation results are in a close agreement with the theoretical analysis which is done in MATLAB. Furthermore, the process, voltage and temperature variation simulations are done to study the effect of non-idealities on the performance of the proposed filter. It is shown that the simulation results justify a 4.8%, 0.8% and 20% variations of the centre frequency for process, voltage and temperature, respectively. Finally, Monte-Carlo, noise and transient simulations are done to justify the good performance of the proposed filter performance.     

Switched-capacitor resonator structure with improved performance

A novel switched-capacitor resonator circuit is proposed. Its centre frequency is insensitive to the finite bandwidth and gain of the opamps used     

一种片内集成飞电容的自适应开关电容DC-DC

提出一种电容片内集成、高效率升压模式的DC-DC电源管理芯片,较普通结构相比,文中提出的电路结构具有6组2×,3组3×,2组4×升压模型共11种工作模式,并具有低纹波等优点。通过MIM电容与积累型NMOS电容串联的方式,提高单位面积容值,使得总电容面积大幅减小。采用SMIC 0.18μm CMOS工艺,利用Cadence工具对电路进行仿真验证,所提出自适应开关电容升压电路,在输出电压为3 V时,其效率最高可达到83.6%。在开关频率为20 MHz时,输入电压范围为1~1.8 V,所需总片内集成电容总面积为900 μm×900 μm,输出电压纹波＜40 mV     

一种应用开关电容分压的电源电压检测电路

提出了一种基于标准CMOS工艺的电压检测(Voltage Detector, VD)电路,具有高集成度、低功耗、检测点多档位可调节的特点。开关电容(Switched Capacitor, SC)电路仅需一个低频时钟即可提供准确的电源分压,在低功耗应用中可以有效替代传统电阻分压。在3.3V电源电压的MCU应用中,电压检测电路仅消耗几百nA的电流,对时钟变化不敏感（低频时钟频率变化范围4 kHz~40 kHz）,并且响应时间在一个时钟周期内     

Electronically tunable current-mode biquad filter employing CCCDTAs and grounded capacitors with low input and high output impedance

In this study, a single-input multiple-outputs current-mode analog biquadratic filter, based on current controlled current differencing transconductance amplifier (CCCDTA) is presented. The proposed filter uses two CCCDTAs and two grounded capacitors without any external resistors, which is well suited for integrated circuit implementation. The filter simultaneously gives 3 standard transfer functions, namely, lowpass, highpass and bandpass filters with independent control of quality factor and pole frequency by electronic method. By summing of I_HP and L_LP, the notch filter can be also achieved. Moreover, the circuit has low input and high output impedance which would be an ideal choice for cascading in current-mode circuit. The PSPICE simulation results are included verifying the workability of the proposed filter. The given results agree well with the theoretical anticipation.     

Switched-capacitor bandpass filter with quasi-continuous digitalQ-factor tunability

A second-order switched-capacitor (SC) bandpass filter with very wide Q-factor programmability range, is presented. Although the Q-factor is controlled by digitally varying the effective sampling frequency of an SC branch, quasi-continuous programmability is provided. Experimental results from a 0.8 μm CMOS integrated prototype demonstrate the versatility of the proposed technique     

Switched-capacitor integrator with reduced sensitivity to amplifier gain

A new switched-capacitor integrator with low sensitivity to finite amplifier gain is described. The circuit is simple, requiring very little extra chip area as compared to the uncompensated integrator. It is compared with previously proposed finite gain compensated switched-capacitor integrators.     

Single FDCCII-based mixed-mode biquad filter with eight outputs

The transconductance and the transresistance modes might act as the bridge transferring from voltage-mode to current-mode and vice versa, respectively. A novel mixed-mode (including voltage, current, transconductance, and transresistance modes) biquad filter with one input and seven outputs or two inputs and eight outputs is presented. The proposed filter structure only uses a single fully differential current conveyor (FDCCII), three resistors and two grounded capacitors, which are the least components necessary for realizing voltage, current, transresistance modes all five standard filter functions and transconductance-mode band-pass, high-pass filter functions from eight output terminals. Moreover, the new mixed-mode biquad filter still enjoys (i) the employment of two grounded capacitors (attractive for absorbing shunt parasitic capacitance and ideal for IC implementation), (ii) orthogonal control of ω₀ and Q (easy for tunability), and (iii) high output impedance of three current outputs (good for cascadability). H-Spice simulation results verify the theoretical analysis.     

High-Q SC biquad with a minimum capacitor spread

Realising SC biquads with high Q values normally results in a high capacitor spread. This means, for MOS circuits, a correspondingly large increase of the total chip area. In the letter, we describe a circuit that allows the realisation of high-Q filters with a minimum capacitor spread resulting in more accurate capacitor ratios and a small overall chip area.     

Parallel-path biquad active-RC oscillator with enhanced harmonicrejection

A biquad active-RC oscillator is described and a linear analysis given which shows that harmonics injected within the feedback loop are multiplied by a factor which is inversely proportional to the effective open-loop Q-factor Q₀. Experimental results show that distortion is low at high Q₀ values even when saturated operation of the main gain-producing op amp is allowed     

Switched-capacitor discrete Fourier analyser with window function circuit

An analogue window function circuit is realized by using switched-capacitor techniques. In order to verify the effect of this window, a novel switched-capacitor analogue discrete Fourier analyser is proposed. The window function circuit is included in this analyser as the ratios of capacitances. This switched-capacitor discrete Fourier analyser is very simple in construction, namely, only two elemental circuits based on the integral feedback capacitance circuit are connected in series. Agreement between the experimental and the theoretical values is confirmed.     

Switched-capacitor lossless discrete differentiator with modified sample-and-hold sequence

For a design of a stray-insensitive switched-capacitor lossless discrete differentiator, a fundamental differentiator circuit and a special sample-and-hold sequence are proposed.