Self-heating characterization and extraction method for thermal resistance and capacitance in HV MOSFETs

This letter reports on the self-heating effect (SHE) characterization of high-voltage (HV) DMOSFETs and the accurate extraction of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/) needed for advanced device and IC simulation. A simple pulsed-gate experiment is proposed and the influence of its parameters (pulse duration and duty factor) are analyzed. It is demonstrated that in our 100 V DMOSFET, SHE is cancelled by using pulses with duration less that 2 /spl mu/s and duty factor lower that 1:100. The new extraction method exploits analytical modeling and dedicated extraction plots for thermal resistance and capacitance using the measurements of output characteristics at various applied pulses and the gradual reduction of SHE with pulse duration and duty factor. Both R/sub TH/ and C/sub TH/ are extracted in saturation region considering their dependence on SHE and external temperature. In DMOSFETs, the thermal resistance is shown to be a significant linear function of the device temperature (in our device, R/sub TH/ could increase by more than 100% over 100/spl deg/C). The thermal capacitance appears to decrease with the injected power and shows a plateau at high V/sub D/. SPICE simulations with the extracted thermal network R/sub TH/-C/sub TH/ circuit are finally used to fully validate the proposed method.     

Analytical threshold voltage model for short channel double-gateSOI MOSFETs

Solving a two-dimensional (2-D) Poisson equation and assuming the minimum potential determines the threshold voltage, V_th, we derived a model for V_th of short channel double-gate SOI MOSFETs, and verified its validity by comparing with numerical data. We evaluated the threshold voltage lowering, ΔV_th, and subthreshold swing (S-swing) degradation with decreasing gate length L _G, and showed that we can design a 0.05-μm-L_G device with ΔV_th of less than 50 mV and an S-swing of less than 70 mV/decade if 10-nm-thick SOI is available     

Modelling the threshold voltage of short-channel silicon-on-insulator MOSFETs

A simple analytical model for the threshold voltage of short-channel, thin-film, fully-depleted silicon-on-insulator MOSFETs is presented. The model is based on the analytical solution for the two-dimensional potential distribution in the silicon film, which is taken as the sum of the long-channel solution to the Poisson equation and the short-channel solution to the Laplace equation. The model shows close agreement with numerical PISCES simulation results. The equivalence between the proposed model and the parabolic model of Young (1989) is also proven.<>     

Observation of MOSFET degradation due to electrical stressingthrough gate-to-source and gate-to-drain capacitance measurement

The authors present observations of changes in the gate capacitances of a MOSFET as a result of hot-carrier stressing and propose capacitance measurement as a method for evaluation of trapped charge. The effect of hot-carrier stressing on 2-μm effective channel length n-channel MOSFETs was monitored by measuring the gate-to-source capacitance and the gate-to drain capacitance. It was found that after electrically stressing a junction of the transistor, capacitances associated with the stressed junction were reduced, whereas the capacitances of the unstressed junction were found to have increased. The observation is explained in terms of the change in channel potential near the stressed junction due to negative trapped charge     

Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs

Quantum-mechanical (QM), or carrier energy-quantization, effects on the subthreshold characteristics, including the threshold voltage (V/sub t/), of generic undoped double-gate (DG) CMOS devices with ultrathin (Si) bodies (UTBs) are physically modeled. The analytic model, with dependences on the UTB thickness (t/sub Si/), the transverse electric field, and the UTB surface orientation, shows how V/sub t/ is increased, and reveals that 1) the subthreshold carrier population in higher-energy subbands is significant, 2) the QM effects in DG devices with {110}-Si surfaces, common in FinFETs, are comparable to those for {100}-Si surfaces for t/sub Si/>/spl sim/4 nm, 3) the QM effects can increase the gate swing, and (iv) the QM effects, especially for t/sub Si/相似文献   

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

New method for extraction of effective channel length in submicron MOSFETs

A new method for effective channel length extraction in submicron MOSFETS is presented. It is based on measurements of the saturation voltage V/sub DSAT/ in devices with different channel lengths. The method has been tested using submicron double diffused drain (DDD) MOS devices.<>     

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.     

A capacitance method to determine the gate-to-drain/Source overlap length of MOSFET's

A method is described which uses accurate measurement of gate-to-drain/source overlap capacitances to determine the gate-to-drain/ source overlap length for process control as well as device characterization. The method might also be a useful analytical tool in studying lateral dopant diffusion. Using this technique, the variation in overlap length of MOSFET's in a 4-in wafer is mapped. It is found that a significant spread of the overlap exits and is attributable to the implant shadowing by the polysilicon gate.     

A new approach to extract the threshold voltage of MOSFETs

A new method is presented to extract the threshold voltage of MOSFETs. It is developed based on an integral function which is insensitive to the drain and source series resistances of the MOSFETs. The method is tested in the environments of circuit simulator (SPICE), device simulation (MEDICI), and measurements     

CMOS voltage reference based on threshold voltage and thermal voltage

A fully CMOS based voltage reference circuit is presented in this paper. The voltage reference circuit uses the difference between gate-to-source voltages of two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining this voltage difference and the extracted threshold voltage of a saturated MOSFET which has a negative temperature coefficient. This circuit, implemented in a standard 0.35-μm CMOS process, provides a nominal reference voltage of 1.361 V at 2-V supply voltage. Experimental results show that the temperature coefficient is 36.7 ppm/°C in the range from −20 to 100°C. It occupies 0.039 mm² of active area and dissipates 82 μW at room temperature. With a 0.5-μF load capacitor, the measured noise density at 100 Hz and 100 kHz is 3.6 and 2 5 \textnV/?{\textHz} , 2 5\,{\text{nV}}/\sqrt {\text{Hz}} , respectively.     

Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations

In this paper, we investigate random doping fluctuation effects in trigate SOI MOSFETs by solving the three-dimensional (3D) Poisson, drift-diffusion and continuity equations numerically. A single doping impurity atom is introduced in the undoped channel region of the device and the resulting shift of threshold voltage is measured from the simulated I–V characteristics. This enables the derivation of the threshold voltage shift (ΔV_TH) for any arbitrary location of the doping atom in the transistor. Based on an analysis of a sub-20 nm trigate MOSFET device, we find that the typical variation of V_TH per doping atom is a few tens of mV. Inversion-mode (IM) trigate devices are more sensitive to the doping fluctuation effects than accumulation-mode (AM) devices. The threshold voltage shift arising from doping fluctuations is maximum when the doping atom is near the center of the channel region, which means the original SOI film doping, the random contamination effects or any other impurity doping in the channel region is more important than atoms introduced in the channel by the S/D implantation process for sub-20 nm transistors.     

Measurement and modeling of the sidewall threshold voltage ofmesa-isolated SOI MOSFETs

Five-terminal silicon-on-insulator (SOI) MOSFETs have been characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with the body bias at the front and back interfaces can be explained by the standard bulk body effect equation. However, the threshold voltage shift at the sidewall is smaller than predicted by this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model that accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation is discussed. The model makes it possible to measure the sidewall threshold even when it is larger than the front threshold voltage     

Calculations on a method for measurement of capacitance changes

A method is described and analysed for measuring accurately small changes in capacitance. It employs a ramp signal applied to a bridge circuit and measures the unbalanced signal on an oscilloscope. The method lends itself to remote operation and operation in an intermittently electrically noisy environment. The feasibility of such measurements is confirmed experimentally.     

A self-consistent analytic threshold voltage model for thin SOI n-channel MOSFETs

An accurate analytical threshold voltage model is presented for fully-depleted SOI n-channel MOSFETs having a metal-insulator-semiconductor-insulator-metal structure. The threshold voltage is defined as the gate voltage at which the second derivative of the inversion charge with respect to the gate voltage is maximum. Since the inversion charge is proportional to the drain current at low bias, the model is self-consistent with the measurement scheme when the threshold voltage is measured as the gate voltage at which the variation of the transconductance at low drain bias is maximum. Numerical simulations show good agreement with the model with less than 3% error.     

Electric potential and threshold voltage models for double-gate Schottky-barrier source/drain MOSFETs

The threshold voltage, V_th of a double-gate (DG) Schottky-barrier (SB) source/drain (S/D) metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. An analytic expression for surface potential is obtained by using Gauss's law and solving Poisson's equation, the results of which are compared with simulations, and good agreement is observed. Based on the potential model, a new definition for V_th is developed, and an analytic expression for V_th is obtained, including quantum mechanical effects and SB lowering effect. We find that V_th is very sensitive to the silicon body thickness, t_si. For a device with a small t_si (<3 nm), V_th increases dramatically with the reduction of t_si. V_th decreases with the increase of the back-gate oxide thickness, and with the increasing of the drain bias. All the results can be of great help to the ultra-large scale integrated-circuit (ULSI) designers.     

Back gate effects on threshold voltage sensitivity to SOI thicknessin fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide     

A new boron implantation model suitable for analytical modeling of threshold voltage of MOSFETs

The boron implantation profile in silicon is usually simulated by the Pearson-IV distribution function with some modifications, as in SUPREM. But this function is complex from the point of view of analytical modeling. New functions which fit very well with SUPREM simulated implantation profiles for boron in silicon have been proposed in this paper. These functions, being analytically integrable, allow us to formulate accurate analytical models of threshold voltages of MOSFETs with implanted channels. In this paper models for the threshold voltages of both long channel and short channel NMOSFETs have been presented. For the long channel case, the results agree very well with those obtained from numerical computations with considerable saving of computation time. The results of the short channel model also show good agreement with available experimental data.