Cellular automata-based built-in self-test structures for VLSI systems

Some of the fundamental algebraic properties of hybrid additive, null-bounded, cellular automata (HACA) are presented. Simple HACA have been obtained by spatially alternating additive rules 90 and 150 (in Wolfram's notation). The use of such HACA for on-chip pseudorandom test pattern generation is also described. The great advantage of HACA over linear feedback shift registers (LFSR), as their size increases, is the fact that HACA display locality and topological regularity, important attributes for VLSI implementation.<>     

内建自测试的测试生成方法研究

内建自测试（BIST）方法是目前可测试性设计（DFT）中应用前景最好的一种方法,其中测试生成是关系BIST性能好坏的一个重要方面。测试生成的目的在于生成尽可能少的测试向量并用以获得足够高的故障覆盖率,同时使得用于测试的硬件电路面积开销尽可能低、测试时间尽可能短。内建自测试的测试生成方法有多种,文中即对这些方法进行了简单介绍和对比研究,分析了各自的优缺点,并在此基础上探讨了BIST面临的主要问题及发展方向。     

A VLSI structure forX(modm) operation

High-computing speed and modularity have made RNS-based arithmetic processors attractive for a long time, especially in signal processing, where additions and multiplications are very frequent. The VLSI technology renewed this interest because RNS-based circuits are becoming more feasible; however, intermodular operations degradate their performance and a great effort results on this topic. In this paper, we deal with the problem of performing the basic operationX(modm), that is the remainder of the integer divisionX/m, for large values of the integerX, following an approximating and correcting approach, which guarantees the correctness of the result. We also define a structure to computeX(modm) by means of few fast VLSI binary multipliers, which is exemplified for 32-bit long numbers, obtaining a total response time lower than 200 nsec. Furthermore, such a structure is evaluated in terms of VLSI complexity and area and time figuresA=?(n ² T _m ² ) andT=?(T _M ) for the parameterT _M in \([\log n,\sqrt n ]\) are derived. A simple positional-to-residue converter is finally presented, based on this structure; it improves some complexity results previously obtained by authors.     

Design of universal test sequences for VLSI

A test sequence is called(s,t)-universal if it exercises every function depending on t or fewer inputs on a very large scale integration (VLSI) chip withsinputs. Randomized and deterministic procedures are deseribed for the design of(s,t)-universal sequences and for the signature analysis of the test outputs.     

Alternative built-in self-test (BIST) structures for analogue circuit fault diagnosis

To increase the number of test points, while still keeping low pint overhead, an alternative built-in self-test (BIST) structure using current copiers is presented. The BIST structure allows simultaneous sampling of either voltage or current test data at various test points and shifting the data for fault diagnosis and testing.<>     

A VLSI structure forX(modm) operation

High-computing speed and modularity have made RNS-based arithmetic processors attractive for a long time, especially in signal processing, where additions and multiplications are very frequent. The VLSI technology renewed this interest because RNS-based circuits are becoming more feasible; however, intermodular operations degradate their performance and a great effort results on this topic. In this paper, we deal with the problem of performing the basic operationX(modm), that is the remainder of the integer divisionX/m, for large values of the integerX, following an approximating and correcting approach, which guarantees the correctness of the result.We also define a structure to computeX(modm) by means of few fast VLSI binary multipliers, which is exemplified for 32-bit long numbers, obtaining a total response time lower than 200 nsec. Furthermore, such a structure is evaluated in terms of VLSI complexity and area and time figuresA=(n ² T _m ² ) andT=(T _M ) for the parameterT _M in are derived. A simple positional-to-residue converter is finally presented, based on this structure; it improves some complexity results previously obtained by authors.This work has been supported by the National Program on Solid-State Electronics and Devices of the Italian National Research Council.     

Basic technology for VLSI (part II)

This paper describes some of the recent work in the field of basic technology at VLSI Cooperative Laboratories. In microfabrication technology, a pair of high-speed electron-beam pattern delineators, electron-beam mask inspection, a pair of electron-beam projection systems, an X-ray lithography system, and electron-beam and X-ray resists are described. Thermally induced microdefects in silicon crystal are analyzed. A plasma etching system, basic testing and evaluation, and basic devices are also discussed.     

Basic Technology for VLSI (Part II)

This paper describes some of the recent work in the field of basic technology at VLSI Cooperative Laboratories. In microfabrication technology, a pair of high-speed electron-beam pattern delineators, electron-beam mask inspection, a pair of electron-beam projection systems, an X-ray lithography system, and electron-beam and X-ray resists are described. Thermally induced microdefects in silicon crystal are analyzed. A plasma etching system, basic testing and evacuation, and basic devices are also discussed.     

A new register file structure for the high-speed microprocessor

The pipeline operations of the register file in a microprocessor are analyzed in detail. Conventional register files, two-port static RAMs, have two problems in successive write-to-read operations. (1) A read-time error takes place when the transition of the W/R mode and the transition of register address occur simultaneously. (2) A write-time error takes place when the supply voltage is slow. A new register file structure is proposed, which has three address word lines and four data bit lines for each memory cell. This structure enables the independent write and read operations to each other, and can solve the two problems. By using this register file structure, a new 16 bit microprocessor with 250 ns machine cycle time is successfully developed. Several other features of this processor are also explained and discussed.     

A fast wafer-level screening test for VLSI metallization

A method for screening out poor-quality metallizations from VLSI fabrication lines by wafer-level probing is proposed. Theoretical analysis suggests a linear dependence of the metal line conductance on the square of the current density, at thermal equilibrium. The limit to this linearity for ideally perfect metallizations occurs at the metal melting point, at which there is a sudden decrease in the conductance value to zero. In real interconnects, nonidealities such as localized defects or nonuniform surrounding dielectric at isolated points could lead to a deviation of the conductance from ideal expectations. Using this as a diagnostic, a universal methodology for assessing metal quality, independently of the physical parameters of the metal line, is described. Qualitative correlation with electromigration lifetime results is used to validate the method     

Integrated pin electronic for a VLSI test system

Drivers, comparators, active loads, and per-pin timing circuitry for a VLSI test system are placed in two CMOS integrated circuits. This level of integration allows fast, low-capacitance pin electronics to be manufactured at relatively low cost. Novel design and calibration techniques are used to overcome limitations of CMOS technology     

New VLSI architectures for three-level correlators

This paper presents the VLSI architectures for three-level correlator design based on 1-m CMOS technology. The architecture performs very high speed, real-time, three-level cross-correlation of signals. Two architectures, one for serial incoming samples of signals (serial data) and the other for stored signal samples (parallel data), are described in the paper.     

New test structure for nanometer-level overlay andfeature-placement metrology

A new electrical test structure for overlay measurement has been evaluated by replicating arrays of its complementary components from two different photomasks into a conducting film on a quartz substrate. The features resulting from images projected from the first mask were used as a reference grid which was calibrated by the NIST line-scale interferometer. A first subset of the relative placements of the images projected from the second mask, which were derived from the electrical overlay measurements and the reference grid, agreed to within 13 nm with corresponding measurements made directly by the line-scale interferometer over distances up to 13.5 mm. A second comparison made at another substrate location indicated that gradients of projected feature linewidths across the exposure site may need to be measured, and corrected for, in the electrical extraction of overlay     

Built-in self-test (BIST) design of high-speed carry-free dividers

This paper presents the built-in self-test (BIST) design of a C-testable high-speed carry-free divider which can be fully tested by 72 test patterns irrespective of the divider size. Using a graph labeling scheme, the test patterns, expected outputs, and control signals can be represented by sets of labels and generated by a simple circuitry. As a result, test patterns can be easily generated inside chips, responses to test patterns need not to be stored, and use of expensive test equipment is not necessary. Results show that the hardware cost for generating such labels is virtually constant irrespective of the circuit size. For the BIST design of a 64 b C-testable divider, its hardware overhead is less than 5%     

Generating test patterns for VLSI circuits using a geneticalgorithm

The authors present the development of a technique that uses genetic algorithms for the generation of rest patterns that detect single stuck-at faults in combinational VLSI circuits. As the genetic algorithm evolves, an efficient set of test patterns are produced, by searching the solution space for patterns that detect the highest number of remaining faults in the fault list     

Quadruply Self-Aligned MOS (QSA MOS) -- A New Short-Channel High-Speed High-Density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually selfaligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for highconductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F X 2F cell (6 /spl mu/m/sup 2//cell, namely 3 X 2 mm/sup 2//1 Mbit in 1-/spl mu/m rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)     

Design of test sequences for VLSI self-testing using LFSR

Consider a shift register (SR) of length n and a collection of designated subsets of {0,1, . . ., n-1}. The problem is how to add feedback to the SR such that the resulting linear feedback shift register (LFSR) exercises (almost) exhaustively each of the designated subsets and is of small period. Several previously known results for maximum-length LFSR are extended to more general LFSR, and in particular a previously known algorithm is simplified and extended. Applications to the problems of VLSI self-testing are discussed and illustrated     

VLSI芯片制备中的多层互连新技术

在简要介绍多层互连材料的基础上,论述了若干种IC芯片制备中的多层互连技术,包括"Cu线 低k双大马士革"多层互连结构、平坦化技术、CMP工艺、"Cu 双大马士革 低k"技术、插塞和金属通孔填充工艺等,并提出了一些多层互连工艺中的关键技术措施.     

New symmetrical buffer design for VLSI applications

Novel fast buffers by the transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in their structure, therefore the design is straightforward and the well balanced speed can be easily obtained. As compared with prior work, the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer circuit shows 27% and 76% average speed enhancements on propagation delays with only 7.3% average increase in its power consumption.     

New dynamic RAM Cell for VLSI memories

A novel high-alpha-particle-immunity and high-density dynamic RAM cell with readout signal gain is proposed. The cell is composed of a MOSFET for charge transfer, a MOS capacitor for charge storage and a junction FET (JFET) with buried channel under the MOS capacitor. The buried channel is dynamically switched according to whether there is charge-storage or not. The cell has extremely small collection efficiency for charges generated by alpha-particles, and allows a large amount of leakage charges due to its peculiar structure. Thus, it can achieve high packing density.