超深亚微米非对称Halo LDD低功耗新器件的研究分析

提出了一种新的器件结构--非对称Halo LDD低功耗器件,该器件可以很好地抑制短沟效应,尤其可以很好地改善DIBL效应、热载流子效应以及降低功耗等,是低功耗高集成度电路的优选结构之一.分析了非对称Halo LDD器件的主要特性,并将其与常规结构、非对称LDD结构、非对称Halo结构的器件进行了比较并进行了参数优化分析.     

超深亚微米非对称Halo LDD低功耗新器件的研究分析

提出了一种新的器件结构——非对称Halo L DD低功耗器件,该器件可以很好地抑制短沟效应,尤其可以很好地改善DIBL效应、热载流子效应以及降低功耗等,是低功耗高集成度电路的优选结构之一.分析了非对称HaloL DD器件的主要特性,并将其与常规结构、非对称L DD结构、非对称Halo结构的器件进行了比较并进行了参数优化分析.     

漏轻掺杂MOSFET的源漏穿通

测量和分析了1μm LDD MOSFET的穿通特性,与常规结构的MOSFET加以比较.结果表明,LDD结构能够有效地抑制DIBL效应、大幅度地提高短沟道MOSFET的源漏穿通电压.此外,还给出LDD MOSFET源漏穿通机制的定性解释.     

异质栅非对称Halo SOI MOSFET

为了抑制异质栅SOI MOSFET的漏致势垒降低效应,在沟道源端一侧引入了高掺杂Halo结构.通过求解二维电势Poisson方程,为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型,并对其性能改进情况进行了研究.结果表明,新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应,并进一步提高载流子输运效率.新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱,但随Halo区长度非单调变化.解析模型与数值模拟软件MEDICI所得结果高度吻合.     

LDD NMOS器件热载流子退化研究

对LDD(轻掺杂漏)NMOS器件的热载流子退化特性进行了研究,发现LDD NMOS器件的退化呈现出新的特点.通过实验与模拟分析,得出了热载流子应力下LDD NMOS退化特性不同于常规(非LDD)NMOS的物理机制.并通过模拟对此观点进行了验证.     

并五苯薄膜晶体管及其应用

有机薄膜晶体管(TFT)在数据存储、集成电路、传感器诸方面的广泛应用引起了人们极大的兴趣.在有机TFT的研究中,并五苯TFT占有很重要的地位.介绍了并五苯薄膜晶体管的结构、工作原理及其应用,评述了该领域的研究进展,并对其前景进行了展望.     

Halo结构器件研究综述

随着集成电路产业的迅速发展,CMOS工艺已进入≥22nm特征尺寸的研究。讨论了Halo结构在当前工艺尺寸等比例缩小挑战背景下的应用情况。与传统长沟器件结构进行了比较,指出由于短沟效应(SCE)和漏致势垒降低(DIBL)效应需要专门工艺来克服,Halo注入通过在沟道两侧形成高掺杂浓度区,达到对SCE和DIBL进行有效抑制的目的,现已成为备受关注的结构。针对有关Halo的研究内容进行综述,并对其在CMOS工艺等比例缩小进程中所起的作用进行评述,对Halo的发展趋势进行了展望。     

0.8μm CMOS LDD器件可靠性实验和分析

针对实验中发现的亚微米LDD结构的特殊的衬底电流现象和退化现象,进行了二维器件数值模拟,解释了LDD器件退化的原因,最后提出了LDD器件的优化工艺条件。     

轻掺杂漏(LDD)MOSFET的数值模拟

轻掺杂漏(LDD)MOSFET是一种已用在VLSI中的新型MOSFET结构.为了有效地进行LDD MOSFEI的优化设计,我们在二维数值模拟器MINIMOS的基础上,修改了边界条件及输入输出格式,考虑了轻掺杂区的杂质分布,研制成功了一种既适用于常规以MOSFET,又适用于LDD MOSFET的二维数值模拟程序FD-MINIMOS.应用该程序对LDD MOSFET的一系列直流特性模拟的结果表明,不同的轻掺杂浓度对于抑制沟道电场及热电子效应具有不同的效果,为轻掺杂区优化设计提供了重要信息.     

多晶侧壁LDDCMOS工艺技术

LDD结构的形成技术基本上有三种类型:双注入、侧壁掩膜注入及隐埋注入.本文采用多晶硅作侧壁掩膜注入方法形成LDD结构,多晶硅采用SF_σ+Ar进行反应离子刻蚀而成.最后成功地试制了栅宽为2μm的CMOS环振和栅宽为2.5μm的CMOS300门阵列,得到了比较满意的结果.     

A new model for device degradation in low-temperature N-channel polycrystalline silicon TFTs under AC stress

Enhanced device degradation of low-temperature n-channel polycrystalline thin-film transistors (poly-silicon TFTs) under exposure to ac stress has been quantitatively analyzed. This analysis showed that degradation of the device characteristics of a single-drain (SD) TFT is greater under ac stress than under dc stress over an equivalent period. It was found that hot holes are strongly related to this greater severity of degradation. Moreover, a lightly doped drain (LDD) TFT is less strongly affected, and the effect is dominated by accumulated drain-avalanche hot-carrier (DAHC) stress. It was also found that differences between the electric field in the respective channel regions are responsible for the different degradation properties of SD and LDD TFTs. It was shown that the severe degradation under ac stress in an SD TFT is caused by increased DAHC stress, to which electrons emitted from the trap states when the TFT is turned off make significant contributions.     

Electrical characteristics of new LDD poly-Si TFT structuretolerant to process misalignment

A new lightly doped drain (LDD) poly-Si TFT structure having symmetrical electrical characteristics independent of the process induced misalignment is described in this paper. Based on the experimental results, we have established that there is no difference between the bi-directional I_D-V_G characteristics, and a low leakage current, comparable to a conventional LDD poly-Si TFT, has been maintained for this new poly-Si TFT. The maximum ON/OFF current ratio of about 1×10⁸ is obtained for the LDD length of 1.0 μm. In addition, the kink effect in the output characteristics has been remarkably improved in the new TFTs in comparison to the conventional non-LDD single- or dual-gate TFTs     

Effect of LDD structure and channel poly-Si thinning on agate-all-around TFT (GAT) for SRAM's

A lightly doped drain (LDD) structure was used in a gate-all-around TFT (GAT). This suppresses the leakage current much more than the LDD used in a single-gate TFT (SGT), and the current level of the GAT with the LDD is almost the same as that of the single-gate TFT (SGT) with the LDD keeping the GAT's advantage of a high on-current. This is because the LDD effectively relaxes the electric field at the drain edge and reduces the effect of the electric field from the surrounded gate of the GAT. Furthermore, the GAT can suppress individual performance variations. The suppression mechanism of the individual performance variation in a GAT was investigated using a poly-Si TFT simulator. The thinner the channel poly-Si, the smaller the individual performance variation of the TFT. The GAT is more effective in decreasing the individual performance variation for thin channels than the SGT because the GAT can achieve the full depletion of the channel poly-Si with a channel thickness twice as large as the SGT. The GAT is eminently suitable for use in high-density, low-voltage operations, and low-power SRAM's     

源漏轻掺杂结构多晶硅薄膜晶体管模拟研究

采用同型结模型模拟计算了源漏轻掺杂结构的关态漏析电流,同时考虑热电子效应修正漏极电流模拟结果,使漏极电流降低到10^-11A量级,晶体管的开关电流比值达到10^6量级,模拟研究掺杂区浓度和宽度与多晶硅薄膜晶体管开关电流比的变化关系。     

A novel gate-overlapped LDD poly-Si thin-film transistor

We fabricate a new polycrystalline silicon thin-film transistor (poly-Si TFT), called a gate-overlapped lightly doped drain (GO-LDD) TFT, which reduces the leakage current without sacrificing the ON current. A new GO-LDD TFT, of which the electrical characteristics are tolerable to the change of LDD doping concentration, can be easily fabricated by employing the buffer oxide without any additional LDD implantation. The change of ON current due to the misalignment of the LDD region may be eliminated. Experimental results show that the leakage current of the proposed TFT's is reduced by two orders of magnitude, compared with that of conventional nonoffset TFT, while the ON current is not decreased. It is observed that the ON/OFF current ratio is not changed significantly with LDD doping concentration and LDD length     

多晶硅薄膜晶体管液晶显示器件的优化设计

针对多晶硅薄膜晶体管液晶显示器件关态漏电流较大的问题,采用源漏轻掺杂结构以降低关态时电荷的泄漏,增加晶体管的开关电流比值,通过模拟轻掺杂区不同的物理参数,如掺杂浓度及掺杂区宽度等,研究薄膜晶体管的开关电流比值,由此确定像素各部分的尺寸,对液晶显示器件进行优化设计。     

Gate-overlapped lightly doped drain poly-Si thin-film transistorsfor large area-AMLCD

We have fabricated a gate-overlapped lightly doped drain (GO-LDD) polycrystalline silicon thin-film transistor (poly-Si TFT) applicable for large area AMLCD by employing the uniform and low-temperature doping techniques, such as ion shower doping and in situ doping. Experimental results show that the leakage current of the proposed TFT's is reduced by more than the magnitude of two orders, compared with that of conventional nonoffset TFT, while the ON current is scarcely decreased. It is verified by the device simulator that the electron concentration in the LDD region is increased under the ON state and decreased under the OFF state due to the field plate with gate potential over the LDD region. Furthermore, the vertical peak electric field in the LDD region is decreased significantly by the extended field plate potential during the OFF state. It is observed that the gate bias stress degrades significantly the subthreshold slope of the ion shower doped GO-LDD TFT's at the low drain bias but does not degrade the device characteristics of those with in situ doping due to the high-quality TEOS SiO₂ interlayer     

LDD design tradeoffs for single transistor latch-up and hot carrierdegradation control in accumulation mode FD SOI MOSFET's

An experimental study has been conducted of the design tradeoffs of fully-depleted (FD) accumulation mode Silicon-on-Insulator (SOI) MOSFET's with regard to hot carrier reliability, single transistor latch-up and device performance. Three drain designs were considered, using Large-Tilt-Angle Implantation (LATID) for the LDD formation. Structures incorporating 0° angle LDD implant, large angle LDD implant, and no LDD were fabricated, and their hot carrier reliability, single transistor latch-up voltage, and device performance in terms of drive current and speed were determined. Correct interpretation of the experimental results was aided by performing PISCES numerical simulations. It was found that the structure with the best hot carrier reliability (large angle LDD implant) has the worst case latch-up voltage, and the one with the worst hot carrier reliability (no LDD implant) has the best latch-up voltage. Overall good device performance with acceptable hot carrier reliability and latch-up voltage is obtained with the 0° angle LDD implant     

Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

An As-P double-diffused lightly doped drain (LDD) device has been designed and fabricated with a self-aligned titanium disilicide process. The device design was aided by using an analytical one-dimensional model, and analytic results agree well with experimental data on the avalanche breakdown voltage gain and the ratio of substrate current to source current. Threshold voltage and subthreshold characteristics of this device do not deviate from those of a conventional device without LDD and silicide. The drain avalanche breakdown voltage of the LDD device is higher by 2.5 V over the conventional device. Transconductance degradation was observed for the LDD devices due to the inherently high source-drain series resistance of the LDD structure. Substrate current is reduced and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain diffusion and the polysilicon gate to 3 Ω/sq compared with 150 Ω/sq of the unsilicided counterparts. It is also found that larger polysilicon grain size increases the sheet resistance of the silicide gate due to discontinuous titanium disilicide formation on top of polysilicon.