New CMOS Fully‐Differential Transconductor and Application to a Fully‐Differential Gm‐C Filter

A new CMOS voltage‐controlled fully‐differential transconductor is presented. The basic structure of the proposed transconductor is based on a four‐MOS transistor cell operating in the triode or saturation region. It achieves a high linearity range of ± 1 V at a 1.5 V supply voltage. The proposed transconductor is used to realize a new fully‐differential Gm‐C low‐pass filter with a minimum number of transconductors and grounded capacitors. PSpice simulation results for the transconductor circuit and its filter application indicating the linearity range and verifying the analytical results using 0.35 μm technology are also given.     

A New Linearized CCII-Based Fully Differential CMOS Transconductor Used for \hbox {G}_\mathrm{m}-C Active Filters Implementation

The paper presents a new linearized, of high performance, fully differential transconductor, based on class AB second generation current conveyor (CCII) in CMOS technology. The proposed circuit is composed by two positive CCII cells connected in series and a common mode feedback loop. Unlike other CMOS circuits on the basis of CCII reported in the literature, the proposed transconductor cell allows to obtain a higher transconductance value, an improved linearity and operates at high frequency for a 3.3 V supply voltage. As an application, the new transconductor cell in CMOS technology is used for designing a 4th order differential $\hbox {G}_\mathrm{m}$ -C low-pass filters in different approximations (Butterworth and Chebyshev) operating up to 300 MHz cut-off frequency. The simulations performed in 130 nm CMOS process confirm the theoretical results.     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

Low‐Voltage Tunable Pseudo‐Differential Transconductor with High Linearity

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage‐to‐current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 μm CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 μA/V to 165 μA/V) and a total harmonic distortion of ?67 dB at 1 MHz for an input of 1 V_pp and a supply voltage of 1.8 V.     

New CMOS triode transconductor

A new CMOS transconductor is proposed, which is built around two conversion transistors operating in the triode region with their source and drain voltages kept constant. The proposed transconductor has an input swing range of 7 V peak to peak within 1% THD at supply voltages of ±5 V and a large transconductance tuning range. Moreover, it can operate satisfactorily regardless of the transistor body connection     

A Modified CMOS Balanced Output Transconductor with Extended Linearity

A new CMOS balanced output transconductor is presented. The circuit is based on applying the dynamic biasing technique on the floating current source to extend its linearity range. The difference in the biasing currents is compensated to maintain the two output currents balanced by subtracting it at the output nodes. The proposed transconductor is suitable for high frequency applications requiring a wide dynamic range. Rail-to-rail operation is achieved with THD of –33.64 dB. The bandwidth achieved by the transconductor is 240 MHz, and the supply voltage used is ±1.5 V.     

Current-feedback source-degenerated CMOS transconductor with very high linearity

A highly linear current-feedback (CF) transconductor with resistive source-degeneration is developed in CMOS technology. It consists of a differential source follower cascaded with a classical source-degenerated transconductor with its drain current fed back to modulate the bias of the source follower for nonlinearity cancellation, yielding an overall linear transfer function in the circuit. Designed using a 0.35 /spl mu/m CMOS process for a continuous-time delta-sigma application, the CF transconductor achieves a total harmonic distortion better than -80 dB up to 1 MHz for a 0.8 V input differential voltage while the supply voltage is 2.5 V and the power consumption is 3.4 mW.     

A low-voltage, highly linear voltage-controlled transconductor

A low-voltage fully differential, voltage-controlled transconductor is described. The proposed transconductor achieves a wide input/control voltage range, with a highly linear transconductance factor and truly fully differential output currents. The transconductor is used to implement a G/sub m/-C adaptive forward equalizer (FE) for a 125 Mbps wire line transceiver using digital core transistors with channel length of no more than double the feature size in a typical digital CMOS 180-nm process and supply voltage as low as 1.6 V. The adaptive FE enables IEEE 1394b transceivers to operate over UTP-5 cables for up to 100 m in length. The transconductor stage occupies 1945 /spl mu/m/sup 2/ and consumes an average power of 418 /spl mu/w at 125 Mbps and 1.8-V supply.     

A CMOS transconductor with multidecade tuning using balanced current scaling in moderate inversion

A versatile CMOS transconductor is proposed. Voltage-to-current conversion employs a polysilicon resistor and features high linearity over a wide input range and high current efficiency. Programmable balanced current mirrors able to operate in weak or moderate inversion regions provide wide transconductance gain tuning range without degrading other performance parameters like input range and linearity. The transconductor has two degrees of freedom for gain tuning. A 0.5-/spl mu/m implementation achieves a SFDR of 68 dB and a THD of -66.5dB using a dual supply of /spl plusmn/1.3 V with differential input swings equal to 77% of the total supply voltage, transconductance tuning over two decades, and 1.7 mW of static power consumption. Measurements demonstrate that operation in moderate inversion can lead to much less distortion levels than in strong inversion.     

A New Low Voltage CMOS Transconductor for VHF Filtering Applications

In this paper, a new differential input CMOS transconductor circuit for VHF filtering application is introduced. The new circuit has a very high frequency bandwidth, large linear differential mode input range and good common mode signal rejection capability. Using 0.35 m CMOS technology with 3 V power supply, the transconductor has a ±0.9 V linear differential input range with a –54 dB total harmonic distortion (THD) and more than 1 GHz – 3 dB bandwidth. The large signal DC analysis and small signal ac analysis derived by compact equations are in line with SpectreS simulation. A 3rd order elliptic low pass g _m-C filter with a cutoff frequency of 150 MHz is demonstrated as an application of the new transconductor.     

1.5 V tunable Square-Root Domain filter

A novel approach to the design of low-voltage CMOS Square-Root Domain filters is presented. It is based on the large-signal behaviour of a well-known class-AB linear transconductor. A first-order filter is built employing three such transconductors, featuring simplicity and compactness. Measurement results for an experimental prototype in 0.8 /spl mu/m CMOS validate the technique proposed. The filter operates with a single supply voltage of 1.5 V and can be tuned in more than one decade.     

On the use of Nauta's transconductor in low-frequency CMOS gm-C bandpass filters

This paper discusses the use of a transconductor, first proposed by Nauta for high frequency applications, in low frequency CMOS g_m -C bandpass filters. The behavior of the transconductor is examined in detail, showing that the robust implementation of higher-order low-voltage filters is possible for center frequencies in the lower megahertz region. The experimental results are presented of the realization of two prototypes, a 0.6-μm CMOS 18th-order real bandpass filter and a 0.35-μm CMOS 7th-order complex (14th-order bandpass) filter, both with a center frequency of 3 MHz and a passband of 1 MHz. These filters comply with the specifications for the channel-select stage of the Bluetooth short-range radio receiver     

A CMOS transconductor with 80-dB SFDR up to 10 MHz

A CMOS transconductor uses resistors at the input and an OTA in unity-gain feedback to achieve 80-dB spurious-free dynamic range (SFDR) for 3.6-V_pp differential inputs up to 10 MHz. The combination of resistors at the input and negative feedback around the operational transconductance amplifier (OTA) allows this transconductor to accommodate a differential input swing of 4 V with a 3.3-V supply. The total harmonic distortion (THD) of the transconductor is -77 dB at 10 MHz for a 3.6-V_pp differential input and third-order intermodulation spurs measure less than -79 dBe for 1.8-V_pp differential inputs at 1 MHz. The transconductance core dissipates 10.56 mW from a 3.3-V supply and occupies 0.4 mm² in a 0.35-μm CMOS process     

A New CMOS Rail-to-Rail Low Distortion Balanced Output Transconductor

This paper presents a new CMOS transconductor providing low distortion for rail-to-rail signals. The circuit is based on using the anti-phase common source topology with the floating current source to extend its linearity range. The difference in the biasing currents of the floating current source is compensated to maintain the two output currents balanced by subtracting it at the output nodes. The proposed transconductor is suitable for applications requiring wide dynamic ranges. Rail-to-rail operation is achieved with THD less than –37 dB. The bandwidth achieved by the transconductor is 67.5 MHz using a supply voltage of ±1.5 V.     

Highly linear programmable balanced current scaling technique in moderate inversion

A technique to achieve highly linear current scaling in CMOS technologies is proposed. It is based on two balanced electronically programmable current mirrors operating in moderate inversion. The scaling factor can be continuously adjusted in a wide range. This technique can be employed to achieve or to extend gain adjustment in amplifiers. As an application example, a variable-gain differential current amplifier and a tunable transconductor are presented. Measurement results of the transconductor implemented in a 0.5-/spl mu/m CMOS technology validate in silicon the proposed approach.     

A compact tunable CMOS transconductor with high linearity

A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-/spl mu/m CMOS technology show a total harmonic distortion of -54 dB at 100 kHz for an 80-/spl mu/A peak-to-peak output, using a supply voltage of 2 V. It requires 0.07-mm/sup 2/ of silicon (Si) area and features 0.96 mW of static power consumption.     

Low-Power Low-Voltage Class-AB Linear OTA for HF Filters with a Large Tuning Range

This letter presents a new low-voltage class-AB differential linear OTA. The proposed transconductor uses a novel scheme based on two cross-coupled class-AB pseudo-differential pairs biased by a Flipped Voltage Follower [1]. The transconductor has been designed using a 0.8 m CMOS technology to operate at 2 V supply voltage with only 260 W of quiescent power consumption. Simulation results show 90 MHz bandwidth with more than two decades of transconductance tuning range.     

Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic

A very low voltage transconductor for video frequency range applications and compatible with standard CMOS technology is described. In the proposed transconductor, except the DC level shifter circuit (DCLS), the whole transconductor uses the main supply voltage [which can be as low as 1.5 V in a standard 0.6 μm CMOS technology] while the DCLS uses a simple charge-pump circuit as its supply voltage and has a very low current consumption. In addition, proper common-mode sense and charge-pump circuits are developed for this low-voltage application. Meanwhile, some techniques to improve the frequency response, linearity, and noise performance of the proposed transconductor are described. In a standard 0.6 μm CMOS technology and single 1.5 V supply, simulations show that the proposed transconductor futures a THD of −50 dB for 1.4 V_pp and 10 MHz input signal and −60 dB for 1.4 V_pp and 1 MHz signal where the threshold voltage of MOS transistors could be as high as 1 V. Based on the proposed transconductor, a lowpass filter with 700 kHz to 8 MHz programmable cutoff frequency and a bandpass 10.7 MHz second order filter were implemented. Armin Tajalli received the B.Sc. from Sharif University of Technology (SUT), Tehran, Iran, in 1997, and M.Sc. from Tehran Polytechnic University, Tehran, Iran, in 1999. From 1998 he has joint Emad Co. as a senior design engineer were he has worked on several industrial and R&D projects on analog and mixed-mode ICs. He received the award of the Best Design Engineer from Emad Co., 2001, the Kharazmi Award of Industrial Research and Development, Iran, 2002, and Presidential Award of the Best Iranian Researchers, in 2003. He is now working toward his PhD degree at SUT. His current interests are design of high speed circuits for telecommunication systems. Mojtaba Atarodi received the B.S.E.E. from Amir Kabir University of Technology (Tehran Polytechnic) in 1985, and M.Sc. degree in electrical engineering from the University of California, Irvine, in 1987. He received the Ph.D. degree from the University of Southern California (USC) on the subject of analog IC design in 1993. From 1993 to 1996 he worked with Linear Technology Corporation as a senior analog design engineer. Since then, he has been consulting with different IC companies. He is currently a visiting professor at Sharif University of Technology. He has published more than 30 technical papers in the area of analog and mixed-signal integrated circuit design as well as analog CAD tools.     

一种新型的宽线性范围差分电压输入电流传输器及其应用

设计了一种带有共模检测电路的宽线性范围差分电压输入电流传输器(DVCCⅡ).所提出的电路具有动态的长尾电流的差分对,可获得较大的动态线性输入范围.所提出的电路可以得到精确跟随特性和宽线性输入范围,且比较已有电路具有低电压低功耗等特点.采用SMIC 0.18μm工艺,用Spectre对电路进行仿真,电源电压是1.8 V,...     

A Highly Linear Wideband Up-Conversion Differential CMOS Micromixer Using IMD3 Cancellation for a Digital TV Tuner IC

In this letter, a highly linear wideband up-conversion differential CMOS micromixer with a linearized transconductor employing a third order intermodulation (IMD3) cancellation technique for a digital TV tuner IC is proposed and designed. It is fabricated in a 0.18 $mu$ m CMOS process and draws 22 mA from a 1.8 V supply voltage. It shows a voltage gain of more than 6 dB, a noise figure lower than 11.9 dB, an IIP2 of more than 57 dBm, and an IIP3 of more than 18 dBm for the entire input band from 48 to 860 MHz.