用2.5D TSV实现多处理器SiP功能

本项目由Open-Silicon,GLOBALFOUNDRI ES和Amkor三家公司合作完成。两颗28nm的ARM处理器芯片,通过2.5D硅转接板实现集成。芯片的高性能集成通常由晶体管制程提高来实现,应用2.5D技术的Si P正成为传统芯片系统集成的有效替代。Open-Silicon负责芯片和硅转接板的设计,重点在于性能优化和成本降低。GLOBALFOUNDRI ES采用28nm超低能耗芯片工艺制造处理器芯片,而用65nm技术制造2.5D硅转接板。包括功耗优化和功能界面有效管理等概念得到验证。硅基板的高密度布线提供大量平行I/O,以实现高性能存储,并保持较低功耗。所开发的EDA设计参考流程可以用于优化2.5D设计。本文展示了如何将大颗芯片重新设计成较小的几颗芯片,通过2.5D硅转接板实现Si P系统集成,以降低成本,提高良率,增加设计灵活性和重复使用性,并减少开发风险。     

WLAN SOC芯片BX501的FPGA验证平台设计与实现

系统芯片（SOC）设计是以模块复用和软硬件协同设计为基础，基于FPGA的验证平台是一种有效的验证途径。文章讨论了WLANSOC芯片BX501的验证平台的两种实现方案，介绍了采用Xilinx Virtex-Ⅱ系列FPGA的设计实现；同时对SOC设计的FPGA验证问题进行了分析和探讨。     

液晶显示驱动板的设计与实现

分析了两种常用的彩色TFT液晶显示驱动板的系统组成、性能及优缺点，提出了一种基于工业级FPGA的设计方案，成功地研制出一款工业级液晶显示器驱动板，并通过了测试，从性能与成本两方面说明了该方案的优点。     

3×3电视墙数控系统的硬件实现

描述了采用现场可编程门阵列(FPGA)作主控芯片来实现对3×3电视墙的控制,其关键在于图像的分割存储和图像放大的算法以及对时序的严格控制。采用两帧轮换存储方法实现图象分割,并对FPGA所有程序进行了仿真。     

无线通信中的自适应芯片

蜂窝电话厂商正处于进退维谷之地,一方面,市场对手机的需求持续增长。2003年上半年,手机总产量为1.07亿部,比去年同期增长12%。另一方面,蜂窝电话技术也在快速改变。例如,现在日益增多的无线通信标准,如802.11 WLAN协议族、CDMA、GSM、3G等。传统上,对不同的标准,设备需要单独的芯片。提供每种功能一般需要一个芯片,或者在实际中将多个电路系统在物理上合成到一个硅片。在移动设备中,额外的电路增加了成本,占据了额外的空间,增加了电源消耗,也增加了产品的设计时间。现在,厂家使用一种老方法来解决这个问题——自适应芯片,也称为可配置芯片。用这种方法,软件能够在硬件不工作的时候重新设计芯片的物理电路,使每个处理器执行多种功能,这可以在不增加新的芯片的同时增加新的功能。支持者们认为可重配置的芯片可以结合微处理器的可编程性和专用硬件的速度。     

无需TSV的3D芯片叠加

正成就高性能,低成本,薄型化封装设计面对面芯片叠加可以简化封装:使用成熟的铜柱微凸点倒装技术叠加两颗或多颗芯片,而无需昂贵的穿硅孔(TSV)技术近距离芯片互联可以提高性能:实现高带宽,高密度和高功率目标,而无需昂贵的2.5D或3D穿硅孔(TSV)技术优化芯片放置可以实现轻薄化:减薄的子芯片置于倒装母芯片下的凸点阵列环内与母芯片互联,或置于基板BGA阵列环内与基板互联,封装体没有增厚     

用CPLD实现安全可靠的FPGA加密设计

基于SRAM（静态随机存储器）工艺的FPGA即现场可编程门阵列（Field Programmable Gate Array）,每次上电时都需要重新配置.为了防止上电时数据流被非法克隆,CPLD和FPGA内都有一个相同的伪随机码发生器,可以利用CPLD产生伪随机码来加密FPGA.上电配置完时,FPGA处于等待状态,且不能正常工作,此时两个伪随机序列握手比较,相同时,使FPGA工作,否则停止工作.通过对Gollman算法的研究,能达到很好的加密效果,保证了开发者的知识产权不受侵害,在现代电子、通讯等领域得到了广泛的应用.     

基于FPGA的高性能DAC芯片测试与研究

介绍了一种基于现场可编程门阵列（FPGA,field programmable gate array）的高性能数模转换器（DAC,digital to analog converter）性能参数的回路测试方法。以FPGA、DAC和模数转换器（ADC,analog to digital converter）等元器件为硬件测试平台,将待测数字信号转换成模拟信号再转换成数字信号,经过Matlab计算和分析后得到DAC芯片的静态特性参数和动态特性参数。其中失调误差为0.036%,增益误差为3.63%,信号噪声比为58 dB,信号噪声及失真比为57.75 dB,无杂散动态范围为62.84 dB,有效位数为9.3。测试结果表明：测试方法通用性好,精确度高,成本低。     

基于FPGA的实验室常用芯片测试仪

针对电子技术实验无法进行多芯片同时测试的问题,提出了一种基于FPGA和上下位机联动配置技术的智能式多芯片测试方案.该方案实现了同一插槽测试不同芯片和集成电路测试台上多个芯片同时测试的功能.介绍了Verilog硬件描述语言编程下载和上位机控制方法与实现技术,有效解决了实验室常用芯片中不同类型芯片电源管脚上电的难题,利用FPGA器件实现了低功耗和系统可再编程升级,对于提高高校电子技术基础实验的水平和效率具有重要的实用价值.     

用FPGA实现数字有线电视的加解扰

介绍了用FPGA（现场可编程门阵列）器件实现有线电视加解扰功能,分析了两种数字有纡电视加解扰方式的基本原理和实现过程,并对这两种加解扰方式进行了比较。     

3DIC集成与硅通孔(TSV)互连

介绍了3维封装及其互连技术的研究与开发现状,重点讨论了垂直互连的硅通孔（TSV）互连工艺的关键技术及其加工设备面临的挑战．提出了工艺和设备开发商的应对措施并探讨了3DTSV封装技术的应用前景。     

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

Copper plating for 3D interconnects

In this paper we report on Cu plating of through-silicon-vias (TSV-s) using in-house made acidic Cu bath with model additives (SPS, PEG, and JGB). Although the model additives might not be as potent as commercial additives, they have been studied in detail, and their role in Cu plating has been described extensively in scientific literature. This in turn allows deeper insight into how changes in bath composition affect the plating mechanism and Cu via-fill.     

三维集成封装中的TSV互连工艺研究进展

为顺应摩尔定律的增长趋势,芯片技术已来到超越"摩尔定律"的三维集成时代。电子系统进一步小型化和性能提高,越来越需要使用三维集成方案,在此需求推动下,穿透硅通孔(TSV)互连技术应运而生,成为三维集成和晶圆级封装的关键技术之一。TSV集成与传统组装方式相比较,具有独特的优势,如减少互连长度、提高电性能并为异质集成提供了更宽的选择范围。三维集成技术可使诸如RF器件、存储器、逻辑器件和MEMS等难以兼容的多个系列元器件集成到一个系统里面。文章结合近两年的国外文献,总结了用于三维集成封装的TSV的互连技术和工艺,探讨了其未来发展方向。     

Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration

In this paper we will highlight key integration issues that were encountered during the development of the 3D-stacked IC Through Silicon Via (TSV) module and present solutions to achieve a robust copper TSV. Electrical performance of the obtained TSV module is discussed based on a lumped RC model for 3D ring oscillators containing TSVs between bottom and top tiers.     

3D封装及其最新研究进展

介绍了3D封装的主要形式和分类。将实现3D互连的方法分为引线键合、倒装芯片、硅通孔、薄膜导线等,并对它们的优缺点进行了分析。围绕凸点技术、金属化、芯片减薄及清洁、散热及电路性能、嵌入式工艺、低温互连工艺等,重点阐述了3D互连工艺的最新研究成果。结合行业背景和国内外专家学者的研究,指出3D封装主要面临的是散热和工艺兼容性等问题,提出应尽快形成统一的行业标准和系统的评价检测体系,同时指出对穿透硅通孔(TSV)互连工艺的研究是未来研究工作的重点和热点。     

Wafer-level three-dimensional integrated circuits (3D IC): Schemes and key technologies

Schemes and key technologies of wafer-level three-dimensional integrated circuits (3D IC) are reviewed and introduced in this paper. Direction of wafer stacking, methods of wafer bonding, fabrication of through-silicon via (TSV), and classification of wafer type are options for 3D IC schemes. Key technologies, such as alignment, Cu bonding, and TSV fabrication, are described as well. Better performance, lower cost, and more functionality of future electronic products become feasible with 3D IC concept application.     

Magnetic Field Imaging for non destructive 3D IC testing

Due to magnetic fields ability to penetrate through all materials used by the semiconductor industry, a unique ability not found in any other techniques, it has become an important technique for detecting shorts, leakages and opens in multi stacked Through Silicon Via samples. We show in this paper how Magnetic Field Imaging is being used to image the current in a TSV stacked silicon device with a new 3D analysis algorithm of the distance from the top of the stacked device to the current path.     

三维集成电路中硅通孔缺陷建模及自测试/修复方法研究

硅通孔(Through Silicon Via, TSV)是3维集成电路(3D IC)进行垂直互连的关键技术,而绝缘层短路缺陷和凸点开路缺陷是TSV两种常见的失效形式。该文针对以上两种典型缺陷建立了TSV缺陷模型,研究了侧壁电阻及凸点电阻与TSV尺寸之间的关系,并提出了一种基于TSV缺陷电阻端电压的检测方法。同时,设计了一种可同时检测以上两种缺陷的自测试电路验证所提方法,该自测试电路还可以级联起来完成片内修复功能。通过分析面积开销可得,自测试/修复电路在3D IC中所占比例随CMOS/TSV工艺尺寸减小而减小,随TSV阵列规模增大而减小。     

Thinned wafer multi-stack 3DI technology

Wafer scale 3DI technology, so-called wafer-on-a-wafer (WOW), characterized by thinned-wafer stacking and Cu multi-level interconnects, has been developed, and revealed that seven-level multi-wafer stacking is possible. The WOW process differs from the chip-on-a-chip and chip-on-a-wafer processes and can be used for wafer-scale bulk processes, enabling manufacturing from transistor to 3D stacking using wafers. Wafers are thinned down to 20-μm and bonded to the base wafer following back-to-face stacking. Through-silicon-via (TSV) holes with a diameter of 30 μm are formed and etched-off until the lower electrode of Au which is patterned on the underneath wafer. Titanium (Ti) and titanium-nitride (TiN) are formed on a TSV hole as a barrier metal and electrode for the electrochemically plated Cu (ECP-Cu). After ECP-Cu deposition, surface planarization is performed using Surface Planer™. Those wafers are used as a base wafer and multi-stacking is carried out repeatedly. The vertical connection between Cu of TSV and Au is therefore connected with a self-aligned contact and without a bump electrode. The electrical properties of the 242-chain contacts within the wafer were measured and no open failure was found. Adopting the thinned substrates eliminates deep silicon etching, and TSV filling which take a long process time, and reduces the residual stress on the Cu plug. Wafers can be stacked as much as possible in accordance with the degree of integration, and this is expected to be a low-cost and high-integration technology for post-scaling.