超大规模集成电路中基于OCV的时序收敛方法

当芯片设计进入深亚微米,片上工艺偏差(OCV)造成的时序不确定性,成为超大规模集成电路时序收敛中的关键问题,单纯使用传统时序分析方法,已不能完全达到时序收敛的要求。文中首先介绍了静态时序分析方法,阐述了深亚微米下OCV分析对时序收敛的重要性,并提出对OCV问题建模和分析的方法。最后通过一个具体的设计实例,运用基于OCV的时序分析方法达到时序收敛。     

采用微捷码先进的RTL-to-GDSII方法实现高性能的可完全综合微处理器

实现高性能的可完全综合的微处理器要求采用先进的RTL-to—GDSII方法。今天的完整设计流程必须能够权衡考虑性能、功耗和面积等几方面因素,并使用基于强度的准确时延模型,以在全局层级实现对尺寸调整和缓冲的同时优化,最终增强时序可预测性以及结果的质量（QoR）。它也可能涉及到先进的数据路径优化技术的使用,这对于处理器运算集中部分较为有益。为尽可能地减少时序性能下降并实现时序收敛,实现系统必须使用精确的共用路径悲观（CPP）价值来避免串扰,并对所包含的片上变异（OCV）功能使用局部无容限方法。     

28nm制程下多电压设计中AOCV的应用

随着IC工艺技术的进步和发展,我们已经进入28nm工艺制程时代。相对于使用基于设置全局derate值的传统OCV方法,Advanced-OCV方法具有更精准和合理的优势,同时多电压设计已经成为实现低功耗设计的重要手段。因此,本文将基于28nm工艺的设计,介绍AOCV在多电压设计中的时序分析和验证的实际应用以及其带来的优势。     

时钟网格与时钟树设计方法对比研究

基于片上偏差对芯片性能的影响,分析对比了时钟树设计与时钟网格设计,重点分析了时钟网格抗OCV影响的优点,并利用实际电路应用两种方法分别进行设计对比,通过结果分析,验证了理论分析的正确性,证明在抗OCV及时序优化时钟网格方法具有很大的优势。     

Talus 1．2缩短SoC设计周期

Talus1．2可显著缩短片上系统（SOC）的设计周期，让工程师能够结合运用串扰规避、高级片上变异（AOCV）和多模多角（MMMC）分析功能在大型设计或具有200～500个单元的电路模块上实现每天100～150万个单元的设计。Talus已通过了40nm节点芯片的验证，目前应用于复杂的28nm设计。拥有这些最新的增强功能，     

静态时序分析平台

时序分析平台Tekton可在不牺牲精度的前提下较传统工具大幅提高容量,显著缩短运行时间,可以在低成本硬件上有效运行多场景分析。为解决40nm及40nm以下设计团队所面临的时序收敛问题,Tekton支持Advanced0CV（A-OCV）容限降低技术。通过将A-OCV纳入时序收敛流程,设计团队能够最大程度降低可导致投片进度拖延并加大晶粒尺寸的全局悲观容限。     

面向亚阈值的脉冲生成电路设计

基于SMIC 130nm工艺,提出了一种新的面向亚阈值的脉冲生成电路.设计中采用三输入与非门作为延时单元,更好地平衡单元的上拉延时和下拉延时,提高了延时路径的稳定性.新结构脉冲生成电路功能不受工艺偏差和温度变化的影响,在0.3V工作电压,不同工艺角以及-40~125℃温度范围内都能生成稳定可靠的脉冲信号.     

双频双模导航基带芯片的静态时序分析

针对一款双频双模导航基带芯片的ASIC设计,提出一种多异步时钟域的时序约束设计方法,并通过设置虚假路径、多周期路径和修正建立保持时间违例的方法,优化了时序。最终使芯片满足系统时序要求,通过了静态时序验证,为芯片流片提供了可靠保证。     

大容量同步双端口SRAM的仿真方法

根据大容量同步双端口SRAM(静态随机存储器)功能多、时序严格、存储单元数目巨大的特点,提出了一套用于功能复杂的大容量SRAM仿真验证的激励生成和后仿真验证方法。该方法不仅克服了Hsim仿真激励文件编写耗时、不易修改的缺点,而且解决了大容量双端口SRAM后仿真速度缓慢、占用大量硬件资源的问题,在很大程度上缩短了设计周期,保证了投片成功。芯片采用中芯国际0.13μm CMOS工艺流片,实测结果验证了该仿真方法是准确有效的。     

考虑物理布局布线约束的快速时序收敛

本文提供了一种准确高效的多角多模的快速时序收敛ECO解决方案,可以支持复杂So C集成电路层次化设计和多电压域设计。在时序优化过程中不但考虑了物理布局因素约束,还综合考虑了物理布线带来的影响,可以满足20nm先进工艺条件下的设计规则。不但保证了时延计算精度,而且与物理实现PR工具和静态时序分析STA工具保持着很好的一致性。它具有先进的优化算法,灵活的流程控制,能快速实现Setup,Hold,Max-transition等多目标的时序收敛,保证了芯片按时投片生产和产品上市时间。     

Fast Interconnect and Gate Timing Analysis for Performance Optimization

Static timing analysis is a key step in the physical design optimization of VLSI designs. The lumped capacitance model for gate delay and the Elmore model for wire delay have been shown to be inadequate for wire-dominated designs. Using the effective capacitance model for the gate delay calculation and model-order reduction techniques for wire delay calculation is prohibitively expensive. In this paper, we present sufficiently accurate and highly efficient filtering algorithms for interconnect timing as well as gate timing analysis. The key idea is to partition the circuit into low and high complexity circuits, whereby low complexity circuits are handled with efficient algorithms such as total capacitance algorithm for gate delay and the Elmore metric for wire delay and high complexity circuits are handled with sign-off algorithms. Experimental results on microprocessor designs show accuracies that are quite comparable with sign-off delay calculators with more than of 65% reduction in the computation times     

Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling

Sub-threshold designs have become a popular option in many energy constrained applications. However, a major bottleneck for these designs is the challenge in attaining timing closure. Most of the paths in sub-threshold designs can become critical paths due to the purely random process variation on threshold voltage, which exponentially impacts the gate delay. In order to address timing violations caused by process variation, post-silicon tuning is widely used through body biasing technology, which incurs heavy power and area overhead. Therefore, it is imperative to select only a small group of the gates with body biasing for post-silicon-tuning. In this paper, we first formulate this problem as a linear semi-infinite programming (LSIP). Then an efficient algorithm based on the novel concept of Incremental Hypercubic Sampling (IHCS), specially tailored to the problem structure, is proposed along with the convergence analysis. Compared with the state-of-the-art approach based on adaptive filtering, experimental results on industrial designs using 65 nm sub-threshold library demonstrate that our proposed IHCS approach can improve the pass rate by up to 7.3× with a speed up to 4.1×, using the same number of body biasing gates with about the same power consumption.     

ASIC设计中的静态时序分析技术

随着工艺线宽的减小,时序问题开始主导集成电路设计。为了解决全芯片的互连延时,需要全芯片分析和优化。PrimeTime 是Synopsys 公司全芯片和门级静态时序分析工具。PrimeTime 用来分析大型同步数字专用集成电路。静态时序分析是一种彻底的分析、调试、验证设计的方法。     

Efficient algorithms to accurately compute derating factors of digital circuits

Fast, accurate, and detailed Soft Error Rate (SER) estimation of digital circuits is essential for cost-efficient reliable design. A major step to accurately estimate a circuit SER is the computation of failure probability, which requires the computation of three derating factors, namely logical, electrical, and timing derating. The unified treatment of these derating factors is crucial to obtain accurate failure probability. Existing SER estimation techniques are either unscalable to large circuits or inaccurate due to lack of unified treatment of all derating factors. In this paper, we present fast and efficient algorithms to estimate SERs of circuit components in the presence of single event transients by unified computation of all derating factors. The proposed algorithms, based on propagation of error probabilities and shape of erroneous waveforms, are scalable to very large circuits. The experimental results and comparisons with Statistical Fault Injections (SFIs) using Monte-Carlo simulations confirm the accuracy (only 2% difference) and speedup (5–6 orders of magnitudes) of the proposed technique.     

A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits

The correlation between the physical paths of a digital circuit has important implications in various design automation problems, such as timing analysis, test generation and diagnosis. When considering the complexity and tight timing constraints of modern circuits, this correlation affects both the design process and the testing approaches followed in manufacturing. In this work we quantify the diversity of a set of paths (or path segments), let these be critical I/O paths, error propagation paths for various fault models, or paths traced for diagnostic purposes. Circuit paths are encoded using Zero-Suppressed Binary Decision Diagrams (ZBDDs); the proposed method consists of a sequence of standard ZBDD operations to provide a measure of the overlap of the paths under consideration. The main contribution of the presented method is that, path or path segment enumeration is entirely avoided and, hence, a large number of paths can be considered in practical time. Experimentation using standard benchmark circuits demonstrates the effectiveness of the approach in showing the difference in path correlation between various critical I/O path sets as well as propagation paths during test application.     

混合模式下详细布局算法的时延优化策略

在集成电路物理设计中,布局是提升电路时延性能的关键阶段。对混合单元模式的详细布局采取二段式的时延优化策略,以此提高布局质量。在合法化阶段,代价函数中采用增加时延权重因子的方法来调整单元的移动策略,使单元分布更有利于时延。在优化阶段,对关键路径上单元的位置进行评价,试探性地对这些单元进行位置微调,在减少关键路径时延的同时避免对布局产生大的扰动,进一步优化了时延。实验结果表明,二段式时延优化策略能够在线长代价较小的情况下有效地提升电路性能。     

Timing slack optimization approach using FPGA hybrid routing strategy of rip-up-retry and pathfinder

To improve the path slack of Field Programmable Gate Array （FPGA）, this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a col- location table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized （reduced） by 85.8% on average compared with the Versatile Place and Route （VPR） tim- ing-driven routing algorithm, while the run-time is only increased by 15.02% on average.     

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

Power supply noise and crosstalk are the two major noise sources that are pattern dependent and negatively impact signal integrity in digital integrated circuits. These noise sources play a greater role in sub-65nm technologies and may cause timing failures and reliability problems in a design; thus must be carefully taken into consideration during test pattern generation and validation. In this paper, we propose a novel method to evaluate path-delay fault test patterns in terms of their ability to cause excess delay on targeted critical paths. It quantifies the noises with a pattern quality value (Q) using the activated aggressor gates and nets information. The proposed method offers design engineers a quick approach to evaluate the critical paths in static timing analysis (STA) and silicon to improve timing margin strategies. By evaluating the failed test pattern, the proposed method can be used to help identify the root cause during failure analysis. Simulation results demonstrate the efficiency and effectiveness of the pattern grading procedure.