硅基微波毫米波收发芯片封装结构研究

借助硅基转接板来实现芯片互连的2.5D/3D封装技术是目前广泛应用的一种封装方式,其电磁损耗是影响系统集成的关键问题.以一种基于硅基转接板的封装结构为对象,根据理论分析对硅基转接板进行挖腔预处理.通过对该结构进行建模仿真,得出封装结构的电性能指标.最后利用该结构分别封装一个微带直通线和一款收发芯片,并对实际的电性能进行...     

硅通孔(TSV)转接板微组装技术研究进展

以硅通孔(TSV)为核心的三维集成技术是半导体工业界近几年的研发热点,特别是2.5D TSV转接板技术的出现,为实现低成本小尺寸芯片系统封装替代高成本系统芯片(So C)提供了解决方案。转接板作为中介层,实现芯片和芯片、芯片与基板之间的三维互连,降低了系统芯片制作成本和功耗。在基于TSV转接板的三维封装结构中,新型封装结构及封装材料的引入,大尺寸、高功率芯片和小尺寸、细节距微凸点的应用,都为转接板的微组装工艺及其可靠性带来了巨大挑战。综述了TSV转接板微组装的研究现状,及在转接板翘曲、芯片与转接板的精确对准、微组装相关材料、工艺选择等方面面临的关键问题和研究进展。     

2.5D硅转接板关键电参数测试技术研究

硅转接板是3D IC中实现高密度集成的关键模块,获取其技术参数对微系统的设计至关重要.以实际研制的一种2.5D硅转接板为研究对象,对大马士革铜布线(Cu-RDL)、硅通孔(TSV)关键电参数的测试结构与测试方法进行了研究,并对TSV电参数测试结构的寄生电容进行了分析.研究结果表明,研制的2.5D硅转接板中10 μm×8...     

一种基于硅转接板的高安全芯片集成技术研究

针对芯片面临的侵入式物理攻击和侧信道攻击等安全威胁,结合2.5D硅转接板技术,提出了一种新型的芯片高安全、高密度集成方案.芯片被置于硅转接板的埋置槽中,而在该埋置槽中特地设计了能够实现攻击实时检测的高密度立体化金属屏蔽防护网络.埋置槽采用湿法腐蚀的方法进行制备,具有制造工艺简单、成本低等优点,也能够使得金属屏蔽防护网络...     

高速高密度光电共封装技术

分析了高速高密度光电共封装中2.5D、3D集成技术,提出并验证了2种2.5D光电共封装结构:采用硅转接板的光电共封装和采用玻璃转接板的2.5D结构,经仿真得到在40 GHz工作时可以实现较低的插入损耗,并进行了工艺验证,制备了硅转接板和玻璃转接板样品。还提出了一种新型基于有机基板工艺的3D光电共封装结构,该结构相比其他2.5D和3D结构尺寸更小、更薄,设计更灵活。对该结构进行了工艺验证,制作了光探测器(PD)与跨阻放大器(TIA)共同集成的三维光电共封装样品。     

芯片三维互连技术及异质集成研究进展

集成电路的纳米制程工艺逐渐逼近物理极限,通过异质集成来延续和拓展摩尔定律的重要性日趋凸显。异质集成以需求为导向,将分立的处理器、存储器和传感器等不同尺寸、功能和类型的芯片,在三维方向上实现灵活的模块化整合与系统集成。异质集成芯片在垂直方向上的信号互连依赖硅通孔（TSV）或玻璃通孔（TGV）等技术实现,而在水平方向上可通过再布线层（RDL）技术实现高密度互连。异质集成技术开发与整合的关键在于融合实现多尺度、多维度的芯片互连,通过三维互连技术配合,将不同功能的芯粒异质集成到一个封装体中,从而提高带宽和电源效率并减小延迟,为高性能计算、人工智能和智慧终端等提供小尺寸、高性能的芯片。通过综述TSV、TGV、RDL技术及相应的2.5D、3D异质集成方案,阐述了当前研究现状,并探讨存在的技术难点及未来发展趋势。     

无需TSV的3D芯片叠加

正成就高性能,低成本,薄型化封装设计面对面芯片叠加可以简化封装:使用成熟的铜柱微凸点倒装技术叠加两颗或多颗芯片,而无需昂贵的穿硅孔(TSV)技术近距离芯片互联可以提高性能:实现高带宽,高密度和高功率目标,而无需昂贵的2.5D或3D穿硅孔(TSV)技术优化芯片放置可以实现轻薄化:减薄的子芯片置于倒装母芯片下的凸点阵列环内与母芯片互联,或置于基板BGA阵列环内与基板互联,封装体没有增厚     

后摩尔时代的封装技术

介绍了在高性能的互连和高速互连芯片(如微处理器)封装方面发挥其巨大优势的TSV互连和3D堆叠的三维封装技术。采用系统级封装(SiP)嵌入无源和有源元件的技术,有助于动态实现高度的3D-SiP尺寸缩减。将多层芯片嵌入在内核基板的腔体中;采用硅的后端工艺将无源元件集成到硅衬底上,与有源元件芯片、MEMS芯片一起形成一个混合集成的器件平台。在追求具有更高性能的未来器件的过程中,业界最为关注的是采用硅通孔(TSV)技术的3D封装、堆叠式封装以及类似在3D上具有优势的技术,并且正悄悄在技术和市场上取得实实在在的进步。随着这些创新技术在更高系统集成中的应用,为系统提供更多的附加功能和特性,推动封装技术进入后摩尔时代。     

基于TSV倒装焊与芯片叠层的高密度组装及封装技术

系统级封装（Si P）及微系统技术能够在有限空间内实现更高密度、更多功能集成,是满足宇航、武器装备等高端领域电子器件小型化、高性能、高可靠需求的关键技术。重点阐述了基于硅通孔（TSV）转接板的倒装焊立体组装及其过程质量控制、基于键合工艺的芯片叠层、基于倒装焊的双通道散热封装等高密度模块涉及的组装及封装技术,同时对利用TSV转接板实现多芯片倒装焊的模组化、一体化集成方案进行了研究。基于以上技术实现了信息处理Si P模块的高密度、气密性封装,以及满足多倒装芯片散热与CMOS图像传感器（CIS）采光需求的双面三腔体微系统模块封装。     

基于TSV硅转接板封装结构的力学可靠性分析

TSV硅转接板是3D IC封装技术的一项重要应用,其力学可靠性是影响系统集成的关键问题。以某TSV硅转接板封装结构为对象,采用有限元方法开展了封装、服役过程中应力应变特性和热疲劳寿命研究,分析了基板材料对封装结构力学可靠性的影响,提出了基板材料优选思路。论文提出的分析方法可用作此类封装结构设计优化以及结构力学可靠性初步验证的手段,可以提高设计效率,缩短研制周期。     

用芯片嵌入技术创新移动应用中的2D和3D封装结构

智能移动装置的高速发展正在驱动更先进芯片封装技术的开发,以满足多功能集成和小型化的要求。传统的解决方案,如多芯片模块,可能无法同时满足高密度和小型化需求。而先进的2.5D硅基板TSV解决方案成本太高,特别是,在对成本敏感的消费类市场中不能使用。在这两者之间,芯片嵌入式封装可能是一个理想的解决方案,它不但有较高互联密度,较小封装尺寸,也可以实现多芯片集成。本文着重讨论了主动芯片的嵌入技术:二维扇出封装和三维封装叠加。二维结构包括扇出晶圆级封装和多层板中芯片嵌入,前者基于晶圆形式,后者基于型板形式。不同流程的选择造成成本和成品率的差异,也造成芯片放置时间的先后。本文讨论了"Die-First"、"Die-Mid"和"Die-Last"流程的优劣势。主动(有源)芯片嵌入的三维叠加有着与二维芯片嵌入类似的优势,只是主动芯片嵌入封装体的上端可以另外叠加封装体,以实现真正的SiP结构。本文还讨论了芯片嵌入技术的发展、未来增长、可能的封装形式和将来的路线图。     

基于TSV转接板的3D SRAM单粒子多位翻转效应

为了研究硅通孔(TSV)转接板及重离子种类和能量对3D静态随机存储器(SRAM)单粒子多位翻转(MBU)效应的影响,建立了基于TSV转接板的2层堆叠3D封装SRAM模型,并选取6组相同线性能量传递(LET)值、不同能量的离子(¹¹B与^4He、²⁸Si与¹⁹F、⁵⁸Ni与²⁷Si、⁸⁶Kr与⁴⁰Ca、¹⁰⁷Ag与⁷⁴Ge、¹⁸¹Ta与¹³²Xe)进行蒙特卡洛仿真。结果表明,对于2层堆叠的TSV 3D封装SRAM,低能离子入射时,在Si路径下,下堆叠层SRAM多位翻转率比上堆叠层高,在TSV(Cu)路径下,下堆叠层SRAM多位翻转率比Si路径下更大;具有相同LET值的高能离子产生的影响较小。相比2D SRAM,在空间辐射环境中使用基于TSV转接板技术的3D封装SRAM时,需要进行更严格的评估。     

2.5D封装结构回流焊过程热应力分析

对一种典型2.5D封装结构在回流焊工艺过程的热应力进行仿真。通过对比分析传统热力学仿真方法与基于生死单元技术的热力学仿真方法,研究了计算方法对热应力计算结果的影响。在相同参考温度下,由不同计算方法得到的硅通孔(TSV)转接板应力结果相差不大,从焊球应力结果可推测出,基于生死单元技术的热力学仿真方法考虑了残余应力的累积模拟更适合于回流焊过程的热应力仿真。研究了2.5D封装回流焊过程中参考温度的选择对计算结果的影响,选用最高参考温度作为各个组件的参考温度,通常得到TSV转接板的应力值偏大,模拟的结果会更加偏于激进。通过对2.5D封装结构回流焊过程进行热应力分析,对比分析了计算模拟方法和参考温度的选择对最终计算结果的影响。该方法同样可用于指导其他同类2.5D封装结构应力的计算和分析。     

SoC and SiP, the Yin and Yang of the Tao for the New Electronic Era

“More than Moore” is becoming the password for these coming years. New steps to overcome technology limitations to diffuse, on the same die, different chips to have a complete system have been developed. This approach is called system in package (SiP), a way to have in a package dies of logic, analog, memory, passive components, etc., assembled to obtain a miniaturized board. SiP performances and limitations are here analyzed to understand advantages versus system on chip (SoC). This paper is a discussion about the main items that can lead to the choice of the right approach—SiP or SoC—before a system design start. Three persons attend to our virtual meeting: an SoC technology development manager, expert in microcontroller embedded memories and technology integration; an SiP analog radio-frequency design senior expert; and a moderator that designed embedded memories and now SiP, all involved to understand how to reach a tradeoff among these two approaches. Like for the Yin and Yang, symbol of the equilibrium for the Taoist philosophy, the two opposites divide the circle of the life, with a piece of each in the other.      

The development of effective model for thermal conduction analysis for 2.5D packaging using TSV interposer

The effective model for the orthotropic TSV (Through Silicon Via) interposer in heat conduction for 2.5D IC integration was proposed in this study. The simple parallel model was used in out-of-plane direction to predict the effective thermal conductivity for the TSV interposer. The in-plane effective thermal conductivity for the interposer was derived on basis of heat balances. By introducing the effective orthotropic thermal parameters, the TSV structures can be ignored in the present effective model. The computations using the effective model for TSV interposer and the 2.5D package with interposer were carried out. The results showed that the accuracy of the effective model was above 95% comparing with the real model including TSV structures when the volume ratio of the electroplating copper and the silicon interposer is smaller than 10%. Using the effective model, the parametric studies on the interposer sizes and the thermal conductivities of different materials in the 2.5D package were conducted with higher efficiency. The results showed that the performance and sizes of EMC (Epoxy Molding Compound) and the package substrate are more important than that of internal underfills in heat dissipation of the package with TSV interposer.     

应用于三维封装中的硅通孔技术

随着集成电路日新月异的发展,当半导体器件工艺进展到纳米级别后,传统的二维领域封装已渐渐不能满足电路高性能、低功耗与高可靠性的要求。为解决这一问题,三维封装成为了未来封装发展的主流。文章简要介绍了三维封装的工艺流程,并重点介绍了硅通孔技术的现阶段在CSP领域的应用,以及其未来的发展方向。     

Fast algorithms for test optimization of core based 3D SoC

The use of 3D-IC technology has become quite widespread in designing core-based systems-on-chip (SoCs). Concomitantly, testing of cores and inter-layer through-silicon-vias (TSVs) spanning through different layers of 3D chips has become an important problem in the manufacturing cycle. Testing 3D-SoCs is more challenging compared to their 2D counterparts because of the complexity of their design and power management issues. Also, the test procedure demands substantially more power than what is required in the normal functional mode, and hence, stringent thermal constraints during test need to be fulfilled to safeguard future performance and reliability of the chip. Since the overall 3D infrastructure depends on routing layer assignments, core allocation, and the geometry of TSV locations, these parameters should be given due consideration while designing the test-access-mechanism (TAM) that aims for minimizing overall test time satisfying power and TSV constraints. In this paper, we present a three-stage algorithm for reducing the test time in automated post-bond core-based 3D-SoCs, under a set of given constraints on test power, TAM-width, and the number of available TSVs. The proposed algorithm, when run on several ITC-02 SoC benchmarks, outperforms the algorithms presented in earlier work with respect to CPU-time, and additionally, reduces test time in many instances.     

Mechanical and Electrical Reliability Assessment of Stacking of Ultrathin Chips on Si Interposer Using Back-to-Face Architecture

Chip-to-wafer stacking is a key enabling technology for two and half dimension (2.5D) as well as for three dimension (3D), with technological challenges driven by the increase of the die surface and the number of input/outputs (I/Os) and the reduction of the vertical dimensions. In our investigation, chips were assembled using a back-to-face approach on a silicon interposer containing copper through-silicon vias (TSVs). This technology is based on the realization of a high-topology redistribution layer passing over the dies bonded with the active face up on the interposer by using a polymer layer. This architecture is attractive because of the reduction of the chip thickness to an ultrathin dimension, and can offer substantial advantages in terms of design flexibility and technology cost. In this architecture, chip bonding strategies are compared: several bonding materials were tested either on the die side using die-attach film or on the bottom side of the interposer using wafer-level spin-coated polymers. Then, a novel brick (sequence) of processes consisting of high-topology encapsulation and metallization was fully developed to connect the top dies to the bottom wafer. The resulting structure has been modeled through the temperature cycles seen during fabrication using a thermomechanical finite element modeling (FEM) simulation for different geometries and materials. The results indicate a moderate level of stress in the stacked film layers with some concentration in localized regions of the topology. Electrical tests have also been completed at the wafer level, showing low resistances and high yield at front-side and at the back-side level after TSV exposure. Successful reliability tests have also been carried out and support the good mechanical behavior of this integration.     

Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration

A wide range of requests coming from customer appears to demonstrate the feasibility of the TSV for a large range of via size and via AR either for process point of view or for performances point of view. The main application in the market is the CMOS image sensor with the integration of via at AR1. Now based on this first wafer level package of CMOS Image Sensor (CIS), the integration on the z axe will continue by the wafer lens integration for a continuous form factor and low cost module.First 3Di applications with TSV is entering the market with the via-last approach, more simply to be developed in semiconductor manufacturing in order to secure the 3Di technologies and to promote the 3Di to customers. Then specific design and electrical models will be developed and optimized allowing a fast and prosperous development of the via-first approach.A challenge in the modelisation of the TSV is the understanding of the mechanical impact of the trench and the metal filling on the behavior of the CMOS components and the reliability. These types of researches are progressing in various institutes and are essential for an increasing integration of TSV.Because actually, the technology continues to drive the 3D roadmap, the mechanical and thermal modelisation and 3D design tool need to be more activated to be developed faster in order to optimize the 3D module. Then the electrical testing will be a real challenge to be able to distinguish drift in the right strata, to be able to isolate a via within more than 10000 via in a module. The electrical testing will be strictly linked to mechanical and electrical failure analysis to get feed-back in technology, actual drawback of the 3D development.The cost of the 3Di and the TSV integration is more and more important and looks as a primary driver even if the functionalities increase faster than cost! Some steps have been already identified to be more costly steps: bonding and via filling. Indeed, throughput and material used have a direct impact on the final price.Continuous perspectives of TSV integration are progressing in order to optimise actual applications or to develop new integration. First challenging integration is the interposers with 3D interconnection allowing devices mounting on both side, like passive device integration or building of micro-cooling channels. The main interest of the 3D silicon interposer is the fact that it can connect chips at different locations and sizes, as example memory over digital IC. The usage of silicon as an interposer leads to an increase in the cost, but it will boost performances and reduce power consumption. One other advantage of the introduction of 3D interposer is the simplification of the required substrate implying a better mismatch of CTE lowering the packaging failure.In the wafer level package, TSV is now introduced to reduce the package footprint and mainly simplify the capping of device, similar to that for the MEMS. Indeed by integrating TSV, the capping must only protect the device against external environment, and not also take into account the electrical path in the bond layer degrading the hermiticity performance.To finish this paper, the sentence of Yann Guillou is the right situation: “The (3D) roadmaps need to be based on application requirements and not driven by technology ONLY. 3D Integration with TSV is not a scaling based concept Does it make sense today to think about submicron via diameter or dice thinner than 30 μm for example?” Applications need to take a risk by using 3D TSV technology!     

Induced thermo-mechanical reliability of copper-filled TSV interposer by transient selective annealing technology

Managing the stability of related processes in the integrated manufacturing of three-dimensional integrated circuits (3D-ICs) remains unresolved, especially with regard to the thermo-mechanical behavior of copper filled through silicon via (TSV) interposer during annealing. In this work, transient annealing is successfully applied on the filled copper using only one form of selective heating technology. To address the integration problem, transient thermo-structural coupling analysis using a nonlinear finite element simulation is proposed. Compared with the experimental data, the proposed simulation is found to be highly reliable. Analytical results show that temperature decreases from the top surface of the TSV to other regions within a silicon-based TSV interposer. Stress-induced fracture is common among bonded films, thereby worsening the subsequent mechanical reliability of 3D-IC devices. Moreover, the extent of keep-out zone induced by residual stress of Cu-filled TSV is also defined through the simulation-based mobility gain of nano-scaled devices. In accordance with the results of this investigation, an improvement can be obtained by optimizing the fabrication parameters during annealing. The proposed technology provides a high throughput and reliable processes in TSV manufacturing.