ABF塑封基板叠孔的高可靠结构设计

在塑封倒装焊结构中,有芯基板的布线过孔结构在温度循环载荷下的疲劳开裂是影响其可靠性的重要因素。为提升军用增强型有芯基板的设计可靠性,建立了基于Ansys有限元分析软件的塑封基板叠孔疲劳寿命仿真流程,通过子模型分析方法,预测了叠孔应力集中点的疲劳寿命,研究了叠孔位置、叠孔层数、芯层厚度、布线长度等因素对温度循环可靠性的影响。结果表明,铜布线结构最大应力应变点出现在叠孔底端与布线层连接处,这与实际生产中封装样品的失效模式一致,疲劳寿命仿真结果与实验结果相吻合。芯片对角位置叠孔的疲劳寿命比中心位置叠孔下降约36%。与2层叠孔相比,4层叠孔的疲劳寿命下降约55.6%。芯层厚度每增长0.4 mm,叠孔寿命相较于芯层厚度增长前分别下降约22.1%和27.5%。相较于370μm布线结构中的叠孔,5μm布线结构中叠孔的疲劳寿命下降约22.4%。     

基于高密度有机基板工艺的Ka波段天线设计与制造

与传统集成技术相比,有机基板的多层结构不仅可以集成相控阵天线、叠层微带天线等多款天线,其在布线密度、芯片内埋、封装一体化方面也展现出较大优势。介绍了基于高密度有机基板工艺的Ka波段叠层微带天线设计与制造过程,并通过测试验证了其反射特性。使用有机基板集成天线,有利于实现无线通信系统的小型化,其在通信和雷达探测领域有较大的应用潜力。     

多层陶瓷基板制造新技术

采用CuO浆料为布线导体材料是制造多层陶瓷基板的新技术。应用该技术不仅能彻底除去浆料中的有机粘结剂,而且容易控制各工序中的气氛。制成的Cu多层陶瓷基板性能非常良好,特别适合高速电路等的高密度化应用。制造成本低,有利于批量生产和推广应用。本文概述了CuO多层陶瓷基板材料及其制造技术,分析了各工艺对基板性能的影响,确定出了最佳技术条件。该技术的开发成功,极大地促进了各种电子装置的高密度、超小型化。     

陶瓷多层布线基板的高密度封装

系统的高密度封装或在功能块化方面的进展,都使高性能的小型多层电路基板成为迫切需要的了。作为半导体器件直接装配的多层电路基板,由其性能特点陶瓷多层布线基板引起重视。关于陶瓷多层布线基板的制造方法,特长以及应用方法阐述如下:     

LTCC基板制造及控制技术

低温共烧多层陶瓷(LTCC)基板,具有高密度布线,内埋无源元件,IC封装基板和优良的高频特性,目前在宇航、军事、汽车、微波与射频通信领域得到广泛运用,是MCM技术的关键部件.本文介绍了LTCC基板制造的关键技术和性能控制.     

封装用积层法层压板

本文简要介绍了高密度封装的开发背景、发展趋势和市场．及在现有积层法技术基础上，开发的超高密度插入基板的制作和特点。     

铝阳极氧化技术制作三维铝封装基板

采用铝阳极氧化技术,制作了含有阵列型铝通柱的10.16 cm(4英寸)直径封装基板。由金相显微镜观察:基板的厚度在300μm左右,铝通柱的表面直径约158μm,内部最大直径约473μm。分析结果表明:图形掩膜边缘存在侧向阳极氧化效应,因而造成铝通柱实际为纺锤体结构。由半导体网络分析仪测得铝通柱和铝栅格地之间的绝缘电阻达到1011Ω;通过矢量网络分析仪反推出基板介质在1 MHz下的相对介电常数为5.97。这种三维铝封装基板制作工艺简单、成本低廉,可用于系统级封装领域。     

IC封装无芯基板的发展与制造研究

手持电子产品的薄型化催生了IC封装无芯基板,它不仅比IC封装有芯基板更薄,而且电气性能更加优越。介绍了IC封装无芯基板的发展趋势和制造中面临的问题。IC封装无芯基板以半加成法制造,翘曲是目前制程中的首要问题。翘曲改善主要依靠改变绝缘层材料和积层结构,可用云纹干涉法进行量测,并以模拟为指导加快开发周期。     

氮化铝共烧基板表面焊盘的研究

本文研究了在AlN多层布线共烧基板中，采用Ni作为添加剂的表面焊盘浆料体系中SiO2含量对共烧基板烧结性能的影响。结果表明SiO2的质量分数在0．3％时，AlN多层布线共烧基板的焊接强度达到42MPa，基板的翘曲度小于50μm／50mm。     

氮化铝共烧基板金属化及其薄膜金属化特性研究

大规模集成电路的发展,对芯片之间的互连提出了更高的要求,高端电子系统中高密度封装技术逐渐成为发展的主流。多芯片组件(MCM)是微电子封装的高级形式,它是把裸芯片与微型元件组装在同一个高密度布线基板上,组成能够完成一定的功能的模块甚至子系统。MCM还能够实现电子系统的小型化、高密度化,是实现系统集成的重要途径,在MCM中高密度布线的多层基板技术是实现高密度封装的关键。     

倒装焊器件封装结构设计

倒装焊是今后高集成度半导体的主要发展方向之一。倒装焊器件封装结构主要由外壳、芯片、引脚(焊球、焊柱、针)、盖板(气密性封装)或散热片(非气密性封装)等组成。文章分别介绍外壳材料、倒装焊区、频率、气密性、功率等方面对倒装焊封装结构的影响。低温共烧陶瓷(LTCC)适合于高频、大面积的倒装焊芯片。大功率倒装焊散热结构主要跟功率、导热界面材料、散热材料及气密性等有关系。倒装焊器件气密性封装主要有平行缝焊或低温合金熔封工艺。     

A study on thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assembly for thin chip-on-board (COB) packages

In this work, thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assemblies having various chip and substrate thicknesses for thin chip-on-board (COB) packages were investigated. In order to analyze T/C reliability, shear strains of six flip chip assemblies were calculated using Suhir’s model. In addition, correlation of shear strain with die warpage was attempted.The thicknesses of the chips used were 180 μm and 480 μm. The thicknesses of the substrates were 120, 550, and 980 μm. Thus, six combinations of flip chip assemblies were prepared for the T/C reliability test. During the T/C reliability test, the 180 μm thick chip assemblies showed more stable contact resistance changes than the 480 μm thick chip assemblies did for all three substrates. The 550 μm thick substrate assemblies, which had the lowest CTE among three substrates, showed the best T/C reliability performance for a given chip thickness.In order to investigate what the T/C reliability performance results from, die warpages of six assemblies were measured using Twyman–Green interferometry. In addition, shear strains of the flip chip assemblies were calculated using measured material properties of ACF and substrates through Suhir’s 2-D model. T/C reliability of the flip chip assemblies was independent of die warpages; it was, however, in proportion to calculated shear strain. The result was closely related with material properties of the substrates. The T/C reliability of the ACF flip chip assemblies was concluded to be dominatingly dependent on the induced shear strains of ACF layers.     

Genetic algorithms for defect detection of flip chips

Flip chip packaging technology is widely used in high density assembly and superior performance devices. The solder joints are sandwiched between dies and substrates, leading to the defects optically opaque. Defect inspection of flip chips become more difficult. In this paper, a nondestructive detection method was presented. Ultrasonic excitations were forced on the surface of the flip chips and the raw vibration signals were measured by a laser scanning vibrometer. Eleven time domain features and twenty-four frequency domain features were extracted for analysis. After that, the genetic algorithm was introduced for feature selection and the back propagation network was adopted for classification and recognition. The flip chips were divided into three categories: good flip chips, flip chips with missing solder joints, and flip chips with open solder joints. They are recognized under the features selected by genetic algorithms rapidly and accurately, compared with those under other feature datasets, demonstrating that the approach using genetic algorithms is effective for defect inspection in flip chip packaging.     

用2.5D TSV实现多处理器SiP功能

本项目由Open-Silicon,GLOBALFOUNDRI ES和Amkor三家公司合作完成。两颗28nm的ARM处理器芯片,通过2.5D硅转接板实现集成。芯片的高性能集成通常由晶体管制程提高来实现,应用2.5D技术的Si P正成为传统芯片系统集成的有效替代。Open-Silicon负责芯片和硅转接板的设计,重点在于性能优化和成本降低。GLOBALFOUNDRI ES采用28nm超低能耗芯片工艺制造处理器芯片,而用65nm技术制造2.5D硅转接板。包括功耗优化和功能界面有效管理等概念得到验证。硅基板的高密度布线提供大量平行I/O,以实现高性能存储,并保持较低功耗。所开发的EDA设计参考流程可以用于优化2.5D设计。本文展示了如何将大颗芯片重新设计成较小的几颗芯片,通过2.5D硅转接板实现Si P系统集成,以降低成本,提高良率,增加设计灵活性和重复使用性,并减少开发风险。     

Advanced Packaging: The Redistributed Chip Package

The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond ball grid array (BGA) and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low-k device compatibility. The panel is created by attaching the device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multilayer metal RCP packages have passed 40 to 125 C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

Innovative circuit board level routing designs for BGA packages

Advances in the performance of electronic devices have resulted in high input/output counts both at the chip and the package level, which has led to the development of new packaging technologies that can accommodate these high counts. This paper presents and analyzes a novel method for the placement of ball grid array (BGA) bonding pads and routing wires on printed circuit boards to maximize signal density, which ultimately reduces the number of circuit board layers needed for routing. This method has been termed as the "balls shifted as needed" method and all the ball placement/trace routing designs shown in this paper are based on this method. We also present a performance metric defined as the number of balls routed out divided by the area of package footprint on the circuit board, and we compare various placement/routing schemes using this method.     

The first IA-64 microprocessor

The first implementation of the IA-64 architecture achieves high performance by using a highly parallel execution core, while maintaining binary compatibility with the IA-32 instruction set. Explicitly parallel instruction computing (EPIC) design maximizes performance through hardware and software synergy. The processor contains 25.4 million transistors and operates at 800 MHz. The chip is fabricated in a 0.18-μm CMOS process with six metal layers and packaged in a 1012-pad organic land grid array using C4 (flip chip) assembly technology. A core speed back-side bus connects the processor to a 4-MB L3 cache     

High performance package designs for a 1 GHz microprocessor

This paper describes the architecture and design of an organic land grid array (OLGA) and a flip chip pin grid array (FCPGA) package for a 32 b microprocessor with a clock frequency of 1 GHz and an I/O bus designed to run at 133 MHz. Cost and performance targets and compatibility with existing systems are the key accomplishments of this design project. Issues and implementation details of each of these aspects are discussed and contrasted here. This paper concentrates on the processor performance issues associated with the package routing and power delivery. To overcome high inductance associated with the socket and package pins in the FCPGA package, decoupling capacitors were placed on the underside of the package substrate. This paper discusses an optimal placement scheme for the capacitors and their effectiveness in performance improvement of the system compared to the OLGA package case     

采用热压焊工艺实现金凸点芯片的倒装焊接

金凸点芯片的倒装焊接是一种先进的封装技术.叙述了钉头金凸点硅芯片在高密度薄膜陶瓷基板上的热压倒装焊接工艺方法,通过设定焊接参数达到所期望的最大剪切力,分析研究互连焊点的电性能和焊接缺陷,实现了热压倒装焊工艺的优化.同时,还简要介绍了芯片钉头金凸点的制作工艺.