Analysis of the switching speed of BiCMOS buffer under high current

A nonlinear analytical transient response model that is suitable for BiCMOS driver circuits operating under the Kirk and Van der Ziel effect is presented. The model accounts for both base vertical push-out and lateral stretching phenomena where the forward transit time τ _f has a square law dependence on the collector current. Based on the new transient model, a closed-form BiCMOS delay expression is derived that shows excellent agreement with measured gate delay from a 0.8-μm BiCMOS technology. The comparison is made for a wide range of circuit parameters. The delay model can be used to develop timing analyzers, timing simulators, and circuit optimization tools for ULSI circuit design. As an application of the delay model, a circuit design algorithm is derived to optimize the speed-area performance of the BiCMOS buffers     

A delay model and optimization method of a low-power BiCMOS logiccircuit

A new delay model and optimization method is proposed for a low-power BiCMOS driver. A transient overdrive, base directly-tied complementary BiCMOS logic circuit operates faster than conventional BiCMOS and CMOS circuits for supply voltage down to 1.5 V by using a speed-power-area optimization approach. An analytical delay expression is derived for the first time for a full-swing BiCMOS circuit with short-channel effects. The circuit is simulated with a HSPICE model using 0.8-μm BiCMOS technology with a 6-GHz n-p-n and a 1-GHz p-n-p transistor. The simulation results have verified the analytical results and demonstrated that the circuit can work up to 200 MHz operating frequency for a load capacitance of 1 pF at 1.5 V of supply voltage     

Analysis of BiCMOS buffer for input voltages with finite rise time

A BiCMOS digital logic gate is analyzed for input voltages with a finite rise or fall time. A new gate delay model to account for the input slope is developed. A set of accurate yet simple closed-form delay expressions are derived for the first time in terms of the input signal slew rate as well as circuit and device parameters. SPICE simulations are used to verify the accuracy of the analytical delay model. The BiCMOS circuit is characterized in terms of the input slew rate, the fan-in, fan-out, and the circuit delay constants. The model can be incorporated in timing simulators and timing analyzers for BiCMOS ULSI circuit design     

An accurate analytical BiCMOS delay expression and its applicationto optimizing high-speed BiCMOS circuits

A scheme for optimizing the overall delay of BiCMOS driver circuits is proposed in this paper. Using this optimization scheme, it is found that the delay is minimized when the maximum collector current of the bipolar transistors is equal to the onset of high current effects. Using this assumption, an accurate BiCMOS delay expression is derived in terms of the bipolar and MOS device parameters. The critical device parameters are then identified and their influence on the circuit speed discussed. An overall circuit delay expression for optimizing BiCMOS buffers is derived and a comparison made with CMOS buffers. It is shown that BiCMOS circuits have a speed advantage of 1.7 or an area advantage of about 5 for 2-μm feature sizes. In order to predict the future performance of BiCMOS circuits, a figure of merit is derived from the delay expression. Using the figure-of-merit expression, it is seen that future BiCMOS circuits can keep the speed advantage over CMOS circuits down to submicrometer dimensions under constant load capacitance assumption     

Analysis and optimization of BiCMOS gate circuits

A comprehensive view of an optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed. BiCMOS gate delay, when optimized, is found to be expressed as A+B√F, where F is fanout and A and B are coefficients. Since the coefficients can be extracted by SPICE simulation, the delay prediction can be precise, while keeping the delay formula simple enough for circuit designers to derive useful expressions. A procedure for optimizing BiCMOS gates is studied. BiCMOS gate delay can be calculated quickly and optimized efficiently just by looking up a design table which is obtained from SPICE simulations. The procedure for making the design table is technology-independent. Once obtained, the design table can be applied to any design with the same device technology. A sizing strategy of cascaded BiCMOS buffers is derived from the simple delay model. In a 0.8 μm, 9 GHz, BiCMOS process, a BiCMOS-BiCMOS cascaded buffer is optimized when the scale-up factor between two consecutive stages is e ^2.3(≈10.0). A BiCMOS-CMOS cascaded buffer becomes the fastest when the scale-up factor, e^1.6(≈5.0), is employed. The optimization procedure and the sizing strategy can be used for several variants of the basic BiCMOS gate, because the delay model is based on basic circuit models for the variants     

Influence of device parameters on the switching speed of BiCMOSbuffers

The influence of different MOS and bipolar device parameters on the switching speed of a BiCMOS buffer is described. This influence is studied by looking at the response of a BiCMOS inverter to a step input. Using suitable approximations for the high-level injection effects in the bipolar transistor, mathematical approximations for the response are derived. The approximate responses are compared to those determined by SPICE simulations and the agreement is satisfactory. High-current effects in the bipolar transistor strongly affect the performance. The effects of different bipolar transistor parasitic resistors are investigated, and it is found that only the collector resistance is important. The influence of different emitter sizes on the delay time is studied, and it is shown that for a given area, there is one optimal size ratio for the MOS and bipolar transistors for which the delay is minimum     

Study of BiCMOS logic gate configurations for improved low-voltageperformance

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10°C and sub-2 V at 110°C     

Performance predictions of scaled BiCMOS gates using physicalsimulation

The necessary reduction in supply voltage for future scaled-down BiCMOS technologies will cause a degradation in speed because the base-emitter forward voltage drop is not scaled. The analysis of how the performance difference between BiCMOS and CMOS changes with scaling has been ambiguous in previous work because of insufficient model accuracy. In this work, mixed-level device-circuit simulation with accurate numerical device models, used to predict gate delay, output voltage drop, breakdown voltage and hot-carrier reliability estimates for BiCMOS and CMOS structures with different scaling, is described. A very significant result was that for 0.25-μm feature size the bipolar part of BiCMOS will still contribute to performance if the fan-out is high and if appropriate scaling including doping, supply voltage, vertical dimensions, and lateral dimensions is used     

Evaluation of delay-time degradation of low-voltage BiCMOS based ona novel analytical delay-time modeling

The degradation of delay time of totem-pole BiCMOS, CBiCMOS, and BiNMOS circuits by supply voltage reduction is evaluated by a novel delay-time model. It has been found that base-collector capacitance plays a greater role in determining the delay time than other parasitic capacitances in BiCMOS circuits. It is concluded that when the input signal swings fully from zero to the supply voltage, the minimum supply voltage to guarantee high-speed operation over CMOS circuits is almost the same for the three kinds of BiCMOS circuits. When the input swing is reduced by the base-emitter voltage, however, BiNMOS and CBiCMOS circuits can operate on a lower supply voltage than totem-pole BiCMOS circuits     

Full-swing Schottky BiCMOS/BiNMOS and the effects of operatingfrequency and supply voltage scaling

Novel full-swing BiCMOS/BiNMOS logic circuits which use Schottky diode in the pull-up section for low supply-voltage regime are developed. The full-swing pull-up operation is performed by saturating the bipolar transistor with a base current pulse. After which, the base is isolated and bootstrapped to a voltage higher than V_DD. The BiCMOS/BiNMOS circuits do not require a PNP bipolar transistor. They outperform other BiCMOS circuits at low supply voltage, particularly at 2 V using 0.5 μm BiCMOS technology. Delay, area, and power dissipation comparisons have been performed. The new circuits offer delay reduction at 2 V supply voltage of 37% to 56% over CMOS. The minimum fanout at which the new circuits outperform CMOS gate is 2 to 3. Furthermore, the effect of the operating frequency on the delay of a wide range of BiCMOS and BiNMOS circuits is reported for the first time, showing the superiority of the Schottky circuits     

A 1-Mbit BiCMOS DRAM using temperature-compensation circuittechniques

A temperature-compensation circuit technique for a dynamic random-access memory (DRAM) with an on-chip voltage limiter is evaluated using a 1-Mb BiCMOS DRAM. It was found that a BiCMOS bandgap reference generator scheme yields an internal voltage immune from temperature and V_cc variation. Also, bipolar-transistor-oriented memory circuits, such as a static BiCMOS word driver, improve delay time at high temperatures. Furthermore, the BiCMOS driver proves to have better temperature characteristics than the CMOS driver. Finally, a 1-Mb BiCMOS DRAM using the proposed technique was found to have better temperature characteristics than the 1-Mb CMOS DRAM which uses similar techniques, as was expected. Thus, BiCMOS DRAMs have improved access time at high temperatures compared with CMOS DRAMs     

A 64-bit carry look ahead adder using pass transistor BiCMOS gates

This paper describes a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate. The new pass transistor BiCMOS gate has a smaller intrinsic delay time than conventional BiCMOS gates. Furthermore, this gate has a rail-to-rail output voltage. Therefore the next gate does not have a large degradation of its driving capability. The exclusive OR and NOR gate using the pass transistor BiCMOS gate shows a speed advantage over CMOS gates under a wide variance in load capacitance. The pass transistor BiCMOS gates were applied to full adders, carry path circuits, and carry select circuits. In consequence, a 64-bit two-stage carry look ahead adder was fabricated using a 0.5 μm BiCMOS process with single polysilicon and double-metal interconnections. A critical path delay time of 3.5 ns was observed at a supply voltage of 3.3 V. This is 25% better than the result of the adder circuit using CMOS technology. Even at the supply voltage of 2.0 V, this adder is faster than the CMOS adder     

Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 Vsupply voltage regime

Novel full-swing BiCMOS/BiNMOS logic circuits using bootstrapping in the pull-up section for low supply voltage down to 1 V are reported. These circuit configurations use noncomplementary BiCMOS technology. Simulations have shown that they outperform other BiCMOS circuits at low supply voltage using 0.35 μm BiCMOS process. The delay and power dissipation of several NAND configurations have been compared. The new circuits offer delay reduction between 40 and 66% over CMOS in the range 1.2-3.3 V supply voltage. The minimum fanout at which the new circuits outperform CMOS gate is 5, which is lower than that of other gates particularly for sub-2.5 V operation     

A BiCMOS technology with 660-MHz vertical p-n-p transistor foranalog/digital ASICs

A fully complementary BiCMOS technology based on a 2-μm process designed for 12-V analog/digital applications is described. In this technology, a triple diffused vertical p-n-p transistor and n-p-n bipolar and CMOS devices are integrated in a single chip. A transition frequency of 660 MHz and a collector-to-emitter breakdown voltage of over 15 V have been obtained for the collector-isolated p-n-p transistor by adding only one extra mask to a conventional 2-μm BiCMOS process. The total number of masks is 20 with double-layer metallization. A unity gain frequency of 52 MHz and a DC gain of 85 dB have been obtained for a single-supply operational amplifier with a vertical p-n-p first stage. The propagation delay time for a CMOS two-NAND gate was 1.27 ns driving three loads and 3 mm of metal     

Fault characterization, testing considerations, and design fortestability of BiCMOS logic circuits

The results of a simulation-based fault characterization study of BiCMOS logic circuits are given. Based on the fault characterization results, the authors have studied different techniques for testing BiCMOS logic circuits. The effectiveness of stuck-at fault testing, stuck-open fault testing, delay fault testing, and current testing in achieving a high level of defect coverage is studied. A novel BiCMOS circuit structure that improves the testability of BiCMOS digital circuits is presented     

A 1.5-V full-swing BiCMOS logic circuit

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3-μm BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply     

BiCMOS logic testing

With the anticipated growth of BiCMOS technology for high-performance ASIC design, the issue of testing takes on great significance. This paper addresses the testing of BiCMOS logic circuits. Since many different implementations of BiCMOS gates have been proposed, four representative ones are studied. The adequacy of stuck-at, quiescent current, and delay testing are examined based on circuit level faults. It is demonstrated that a large portion of the defects cannot be detected by common stuck-at or quiescent current tests since they manifest themselves as delay faults. By using the results presented, the test methodologies and the logic families can be ranked based on fault coverage. This ranking can then be used to help decide which BiCMOS solution is proper for a given application     

Accurate delay models for digital BiCMOS

A detailed transient analysis of the MOSFET-BJT combination prevalent in digital BiCMOS gates is presented. The analysis accounts for high-level injection leading to BJT β roll-off, base pushout leading to BJT f_T roll-off, short-channel behavior of the MOS drain current, and parasitic capacitances at the base and output. Based on the transient analysis, a piecewise delay expression is derived that shows excellent agreement with measured gate delay and with SPICE simulated delay. The comparisons are made for a wide range of circuit parameters in the gate, namely, MOSFET/BJT size, load capacitance, and supply voltage for both 1- and 0.6-μm BiCMOS technologies. The model is used to optimally size gates, and to determine circuit and device design guidelines to minimize the delay degradation at reduced supply     

An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

BiCMOS circuit technology for a high-speed SRAM

BiCMOS circuit technology for a high-speed and large-capacity ECL-compatible static RAM (SRAM) is described. To obtain high-speed and low-power operation, a decoder with a pre-main decode configuration having an ECL-interface circuit and a word driver with BiCMOS inverter are proposed. A BiCMOS multiplexer with a single emitter-follower driver is also proposed. An optimization method for memory cell array configuration is presented that minimizes the total delay time and the total power dissipation of SRAMs. Circuit simulation results show that a 64-kbit ECL-compatible SRAM with an access time of less than 7 ns and a power dissipation of less than 1 W is obtainable