A low-voltage switched-current delta-sigma modulator

This paper presents the design of a fully differential switched-current delta-sigma modulator using a single 3.3-V power-supply voltage. At system level, we tailor the modulator structure considering the similarity and difference of switched-capacitor and switched-current realizations. At circuit level, we propose a new switched-current memory cell and integrator with improved common mode feedback, without which low power-supply-voltage operation would not be possible. The whole modulator was implemented in a 0.8-μm double-metal digital CMOS process. It occupies an active area of 0.53×0.48 mm² and consumes a current of 0.6 mA from a single 3.3-V power supply. The measured dynamic range is over 10 b     

Fully Differential Class-AB Log-Domain Integrator

A new fully differential class-AB log-domain integrator is proposed. The structure consists of two non-inverting integrators and an intersection circuit with a common-feedback circuit. The effects of transistor non-idealities and signal path mismatches on the differential integrator are investigated. A 5th-order Chebyshev low-pass filter which can be tuned from 1 to 45 MHz is designed. The validity and stability of the proposed circuits are verified using HSPICE simulations.     

A Current-to-Frequency Converter for Switched-Current Circuits

A current-to-frequency converter using switched-current (SI) circuits is proposed. The SI integrator with a hold-and-reset switch can control integration by the output signals. In the proposed circuit the oscillation frequency can be controlled by the input current, and the circuit is operated in the current domain. This is verified by HSPICE simulations.     

An 8-b, 40 msamples/s switched-current-mode track-and-hold circuiton a BiCMOS sea-of-gates array

A fully differential track-and-hold circuit based on the switched-current processing has been integrated on a fully complementary 1.2 μm-6 GHz BiCMOS sea-of-gates array. It is based on a BiCMOS switched-current memory cell which uses MOS transistors to store the analog information and bipolar transistors to implement the switch. This improves the speed achievable and the distortion compared to a CMOS-only switched-current memory cell. A differential configuration is also presented which made it possible to improve performances such as the hold mode feedthrough (<-67 dB @ 10 MHz) or the pedestal error. The acquisition time for a full scale step is 22 ns, in order to reach the final value within 0.1%. It achieves 8-b precision at a sample-rate of 40 MHz under Nyquist condition, a full scale track-mode bandwidth of 150 MHz and a consumption of 80 mW for a surface of 0.44 mm²     

CMOS switched-current ladder filters

The design and implementation of switched-current (SI) ladder filters is described. The basic current-mode circuits, including the SI differential integrator/summer are developed. The SI integrator/summer is shown to be directly analogous to the switched-capacitor (SC) integrator/summer; thus, all the synthesis techniques developed for the design of SC filters can be used to synthesize SI filters. Signal flowgraph synthesis of SI ladder filters is presented. The nonideal characteristics of SI ladder filters that limit their accuracy are evaluated. Clock-feedthrough and device mismatch induced errors are more severe in the present SI circuit configurations than in SC circuits. A standard digital 2-μm n-well CMOS process has been used to implement two high-order ladder filters. Simulations accurately predict the measured results of the first integrated SI filters. The area and power dissipation are comparable to those obtained with the switched-capacitor technique     

New switched-current integrator

A switched-current integrator configuration with greatly improved insensitivity to transistor mismatch is described. A universal integrator configuration is developed which performs an algorithm identical to the well known switched-capacitor universal integrator. This permits signal flowgraph synthesis of switched-current filters with similar properties to those of their switched-capacitor counterparts.<>     

A design and implementation of fully programmable switched-currentIIR filters

An approach to switched-current filter design based on digital multiply-accumulator and delay blocks is presented. The characteristics of the filter are made fully programmable by simply changing the ratios of the coefficient transistors. To reduce the effect of switch charge injection and channel-length modulation, a high-performance, single-ended differential, switched-current memory cell is developed and used as a basic building block. To reduce the chip area and to maintain the required accuracy of the coefficients, an array consisting of three different sizes of transistors is designed instead of using a unit transistor array as coefficient transistors. An experimental prototype infinite impulse response filter array consisting of six second-order switched-current sections is designed and fabricated with a standard 1.2-μ CMOS process technology. A hard-wiring technique is used to program the filters. The test results show that the characteristics of the filters satisfy the design requirements     

Fully balanced CMOS current-mode circuits

A fully balanced current-mode circuit topology has been developed for analog signal processing applications. The basic building block, a 5-V fully balanced current mirror/amplifier, has been fabricated using a standard 2-μm n-well CMOS process. With a peak signal to bias current ratio i/I=0.5, the open-loop total harmonic distortion was-70 dB. With the addition of sampling switches, the current mirror/amplifier forms a fully balanced switched-current integrator that exhibits first-order cancellation of clock-feedthrough/charge-injection effects. Fully balanced SI ladder filters have been implemented using a 2-μm p-well CMOS process. For a sampling frequency of 128 kHz, the five-pole Chebyshev low-pass ladder filters met design specifications of 0.1-dB passband ripple and 5-kHz bandwidth. The dynamic range was 81.5 dB, and the total power dissipation was 14 mW with V_dd 5 V     

开关电流梯形滤波器的双线性变换设计

本文提出了一种用双线性变换进行开关电流（ＳＩ）梯形滤波器设计的方法。该方法不经ＳＣ滤波器，而直接用提出的ＳＩ模块－双线性／差分（ＢｉＤ）积分器去精确模拟全极点及有限零点ＬＣ原型。从而使滤波器设计步骤及电路结构得到简化。     

Second generation fully differential current conveyor based analog circuits

In this paper, we present a new voltage-mode biquad filter that uses a six-terminal CMOS fully differential current conveyor(FDCCII). The FDCCII with only 23 transistors in its structure and operating at ± 1.5 V, is based on a class AB fully differential buffer. The proposed filter has the facility to tune gain, ωo and Q. A circuit division circuit(CDC) is employed to digitally control the FDCCII block. This digitally controlled FDCCII is used to realize a new reconfigurable fully-differential integrator and differentiator. We performed SPICE simulations to determine the performance of all circuits using CMOS 0.25 μm technology.     

Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper

Low-voltage high-speed switched-capacitor (SC) circuit design without using voltage bootstrapper is presented. The basic building block used for low-voltage SC circuit design is the auto-zeroed integrator (AZI), which can work at both low voltage and high sampling frequency. With this method, two low-voltage SC systems were successfully designed and implemented in 1.2-/spl mu/m CMOS technology. The first one is a fully differential SC bandpass biquad working at 1.5 V and 5.0-MHz clock frequency. The measured Q value is 8.0 at the center frequency of 833 kHz. The second one is a fully differential fourth-order bandpass /spl Delta//spl Sigma/ modulator that also works at 1.5 V and 5.0 MHz. Its measured third-order intermodulation is less than -78 dBc due to the low distortion characteristic of AZI. The measured signal-to-noise ratio of the modulator is 61 dB within the narrow band of 25 kHz centered at 1.25 MHz.     

一种12位开关电流型Σ-△调制器

开关电流电路（ＳＩ）是近年兴起的一种模拟电路。文中引用了新型的两步采样开关电流技术（Ｓ＾２Ｉ）,对该电路中减小时钟馈漏效应的几种方法进行了分析。利用差分平衡结构的Ｓ＾２Ｉ存储单元设计了平衡Ｓ＾２Ｉ积分器,并在此基础上设计出一种平衡差分结构的二阶∑－△调制器。该调制器能够完全与标准ＣＭＯＳ数字工艺兼容。利用标准１．２μｍ数字ＣＯＭＳ工艺的ＨＳＰＩＣＥ模型参数进行了分析,该电路信噪比达到７３．３ｄＢ,     

New Fully‐Differential CMOS Second‐Generation Current Conveyer

This paper presents a new CMOS fully‐differential second‐generation current conveyor (FDCCII). The proposed FDCCII is based on a fully‐differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit operating at a supply voltage of ± 1.5 V, it has a total standby current of 380 µA. The applications of the FDCCII to realize a variable gain amplifier, fully‐differential integrator, and fully‐differential second‐order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS 0.35 µm technology.     

一种适用于D类音频功放的全差分运算放大器

介绍了一种应用于超低EMI无滤波D类音频功放的全差分运算放大器结构,可构成积分器,起滤除高次谐波的作用。该运算放大器采用两级结构来获得高增益,第一级为折叠共源共栅,偏置电路采用反馈结构,给整个运算放大器提供偏置电流,从而提高电路的电源抑制比;采用伪AB类输出级提高运放的瞬态响应,稳定运放输出。仿真结果表明,该电路具有良好的性能:增益为113dB,相位裕度为67°;单位增益带宽为1.9MHz,共模抑制比为160dB,电源抑制比为82.7dB;共模反馈环路增益为120dB,相位裕度为62°。     

Fully differential CMOS CCII based on differential difference transconductor

This paper presents a new CMOS fully differential second-generation current conveyor (FDCCII). The proposed FDCCII is based on a fully differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit is operating at supply voltages of ±1.5 V, it has a total standby current of 380 μA. The application of the FDCCII to realize variable gain amplifier, fully differential integrator, and fully differential second order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS 0.35 μm technology.     

一种新型高性能开关电流存储单元的设计

利用一种新技术,在低压(1.8 V)条件下,设计了一种高性能的开关电流(SI)存储单元电路.该电路通过在基本存储单元基础上增加一个电压反转跟随器电路(FVF),从存储晶体管的输入端直接消除时钟馈通(CFT)误差电压,从而阻止了电流误差的产生,使得输出端的CFT误差电流降为原来的6%,并通过Hspice给出了仿真结果.结果表明所设计的电路方案正确有效.     

SWITCHED-CURRENT FILTER DESIGN USING CASCADED SECTIONS

A new analogue sampled-data active device, named as a switched-current operationalamplifier (SIOA), is presented. The use of active circuit elements may simplify drawing the circuitdiagram significantly greatly and may permit easier analysis and synthesis of SI networks. Anumber of all pole and elliptic (second-or third-order) switched-current (SI) filters are derivedfrom the switched capacitor prototypes. These can be used as simple self-contained filters or asfilter sections in the cascaded realizations of a higher order transfer functions. To illustrate theapproach, a fifth-order low-pass filter is designed.     

用对数域电流模式积分器实现的高频集成滤波器

文本提出了全差动对数域电流模式积分器．该积分器的时间常数受参考偏流控制,其直流增益可达60dB,在高频它具有比较平坦的相频特性。用该积分器设计的二阶滤波器和1dB波纹五阶Chebyshev低通滤波器,计算机仿真显示,“实际”频响特性几乎是理想的．且频率可在很宽的范围内调控．这种滤波器具有很低的THD。     

Design of low-voltage and low-power fully integrated filter based on log-domain current-mode integrator

In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range. The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.     

Novel pseudo-class AB fully differential 3V switched current systemcells

A novel pseudo-class AS low conductance fully differential switched current memory structure with high clock feedthrough (CFT) attenuation, is presented. It is designed with a 3V power supply. An integrator using the proposed structure is also presented with simulation results