Energy proportional streaming spiking neural network in a reconfigurable system

This paper presents a high-performance architecture for spiking neural networks that optimizes data precision and streaming of configuration data stored in main memory. The neural network is based on the Izhikevich model and mapped to a CPU-FPGA hybrid device using a high-level synthesis flow. The active area of the network is configurable and this feature is used to create an energy proportional system. Voltage and frequency scaling are applied to the processing hardware and memory system to deliver enough processing and memory bandwidth to maintain real-time performance at minimum power and energy levels. The experiments show that the application of voltage and frequency scaling to DDR memory and programmable logic can reduce its energy requirements by up to 77% and 76% respectively. The performance evaluation show that the solution is superior to competing high-performance hardware, while voltage and frequency scaling reduces overall energy requirements to less than 2% of a software-only implementation at the same level of performance.     

基于布通率的FPGA装箱算法

提出一种基于FPGA布通率的装箱算法.选择连接因子最小的节点作为种子节点;采用基于布通率的启发式函数来选择最合适的逻辑单元(LE)装箱到可配置逻辑单元(CLB)内部.可以同时减少装箱后CLB之间的线网数和CLB引脚的外部使用率,从而减少布线所需的通道数.该算法和已有算法相比较,线网数和布线通道数都减少约30%. 算法的时间复杂度仍然是线性的.     

SEU sensitivity and large spacing TMR efficiency of Kintex-7 and Virtex-7 FPGAs

Dear editor, The static random-access memory(SRAM)-based field pro-grammable gate arrays(FPGAs)mainly composed of ex-tensive configurable logic blocks(CLBs),hig...     

Universal fault diagnosis for lookup table FPGAs

Focusing on configurable logic blocks in a lookup table FPGA, the authors present universal fault diagnosis procedures that can locate a fault to just one CLB. The complexity of the proposed procedure for FPGAs using block-sliced loading is independent of FPGA array size     

一种全新结构的微控制器--Triscend E5

介绍了一种贯例处理器核、可重构逻辑阵列和ＡＳＩＣ电路的微控制器芯片Ｅ５，对它的特点、体系结构和设计流程做了详细的说明，并且分析了其设计思路。     

可配置的程序设计

可配置的程序设计是为了解决面向对象的程序设计关于接口的局限性而提出来的一种程序设计方法,其优势体现在开发人员可以使用配置文件来更改设置,而不必重编译应用程序,使得业务逻辑分离出来。本文详细介绍了一些应用程序所使用的配置文件,从而体现出可配置的程序设计的优势,程序设计必将沿着该技术路线发展下去。     

Data processing in the firmware systems for logic control based on search networks

It was proposed to use the hardware accelerators for analysis and data processing in the systems of logic control on a chip including the interacting processor system, memory, and configurable logic components. The data processing expected execution of operations over the sets of elements each of which can be activated by software and realized in the hardware in parallel networks admitting, if necessary, pipeline processing. New methods of design and use of the sorting and search networks were proposed, and the results of their theoretical and experimental comparison with the existing networks were presented.     

并行可配置的HEVC熵编码的VLSI结构

提出了一种并行的可配置HEVC熵编码的VLSI结构。通过对HEVC参考软件算法分析,针对HEVC中CABAC编码采用高度并行的语法元素处理方式,设计了针对CABAC中语法元素并行处理的硬件结构。同时采用可配置的PE-Array结构,在提高了吞吐率和计算效率的同时,平衡了VLSI设计中面积过大的问题。在SMIC 0.13μm工艺库下,进行了逻辑综合,系统总门数为16.2 K,片上存储为20.8 KB。在时钟频率300 MHz下,可处理3 840×2 160@30 frame/s的视频序列。     

Baring it all to software: Raw machines

The most radical of the architectures that appear in this issue are Raw processors-highly parallel architectures with hundreds of very simple processors coupled to a small portion of the on-chip memory. Each processor, or tile, also contains a small bank of configurable logic, allowing synthesis of complex operations directly in configurable hardware. Unlike the others, this architecture does not use a traditional instruction set architecture. Instead, programs are compiled directly onto the Raw hardware, with all units told explicitly what to do by the compiler. The compiler even schedules most of the intertile communication. The real limitation to this architecture is the efficacy of the compiler. The authors demonstrate impressive speedups for simple algorithms that lend themselves well to this architectural model, but whether this architecture will be effective for future workloads is an open question     

一种构件化动态软件系统组态模型

在讨论软件构件技术复用现状的基础上,借鉴工业控制领域的组态概念,提出了一种构件化动态软件系统组态模型。其基本思想是：在一定的软件体系结构基础上,用系统的宏观逻辑组态描述联结实现系统具体功能的软件构件,定制组装成完整的应用系统。构件化大大提高软件开发的速度和效率,逻辑和实现的分离明显改善软件系统的灵活性和逻辑可扩充性,系统逻辑组态描述能始终保持软件系统应用和需求的一致性。     

基于Solaris的DCS内嵌式先进控制与优化软件的设计和应用

为加快先进控制与优化在工业领域的应用,设计并完成了一套基于Solaris系统的大型DCS嵌入式先进控制与优化软件,其在数据的高速稳定读写、数据缓存和预处理、算法模块化多线程并行处理、参数高度可配置化、配置文件标准化、统一的日志系统、线程管理以及DCS无缝衔接等方面进行了先进的设计,系统具有很高的通用性和可移植性,可广泛应用于工业控制领域.软件系统在电站锅炉燃烧优化及汽温控制中的应用,获得了非常好的应用效果,显示了极高的稳定性,显著提高了电站自动化水平并收到了良好的经济效益.     

一种面向微处理器验证的分层随机激励方法*

针对日趋复杂的微处理器功能验证,提出一种基于分层思想的受限随机激励产生方法,通过测试层、场景层、功能层和指令层的多层约束,实现随机激励在不同粒度范围的高度可控性,精炼测试空间,加快验证的收敛速度。采用可配置的功能库,将处理器功能行为单元作为随机激励的构建基础,产生逻辑功能与通信接口结合的随机激励,实现系列处理器的验证复用。CKCore处理器验证的实验结果表明,该方法与受限随机激励相比,在功能覆盖率相同的情况下,激励编写量减少60%;在仿真时间相同的情况下,功能和代码覆盖率分别改善10%和5%以上,有效提高处理器验证的质量和效率。     

结构可变更、界面可配置的通用基础信息模型

针对关系数据库设计中潜在逻辑结构变更的需求,利用模板-实例思想,在关系数据库基础上设计实现一套对基础信息统一表达处理模型,以实现新旧逻辑结构数据共存、逻辑结构立即变更立即生效的目的;与通用信息模型相结合,针对广泛自定义输入界面需求,利用表格布局方式和浏览器交互功能,设计实现可配置界面功能;通过配置即可完成逻辑结构定义、输入输出界面编辑功能;模型的原型已应用于某单位人力资源决策辅助系统中。     

Struts异常处理机制研究及应用

Struts是一个优秀的开源框架,不仅在控制逻辑上有良好的表现能力,而且也提供了强大的异常框架。在这个框架下,异常定义和异常处理有许多方式,而自定义的异常类和可配置的异常处理方式成为开发者在处理异常时首选的技术。本文在对Struts中异常处理技术详细分析的基础上给出一个典型的应用案例。     

An introduction to fuzzy answer set programming

In this paper we show how the concepts of answer set programming and fuzzy logic can be successfully combined into the single framework of fuzzy answer set programming (FASP). The framework offers the best of both worlds: from the answer set semantics, it inherits the truly declarative non-monotonic reasoning capabilities while, on the other hand, the notions from fuzzy logic in the framework allow it to step away from the sharp principles used in classical logic, e.g., that something is either completely true or completely false. As fuzzy logic gives the user great flexibility regarding the choice for the interpretation of the notions of negation, conjunction, disjunction and implication, the FASP framework is highly configurable and can, e.g., be tailored to any specific area of application. Finally, the presented framework turns out to be a proper extension of classical answer set programming, as we show, in contrast to other proposals in the literature, that there are only minor restrictions one has to demand on the fuzzy operations used, in order to be able to retrieve the classical semantics using FASP.     

存算解耦合的粗粒度可重构阵列访存结构设计

粗粒度可重构阵列架构兼具灵活性和高效性,但高计算吞吐量的特性也会给访存带来压力.在片下动态存储器带宽相对固定的情况下,设计一种存算解耦合的访存结构.将控制逻辑集成在轻量级的存储空间中,通过可配置的存储空间隔离访存和计算的循环迭代,从而掩盖内存延时,同时利用该结构进行串联和对齐操作,以适配不同的计算访存频率比并优化间接访...     

基于DSP的ARINC429通信板卡设计

针对目前先进飞机自动配电系统的要求,设计了一款扩展性和可靠性好的ARINC429通信板卡.运用FPGA技术完成接口逻辑控制和全局时钟分配(倍频或分频),采用HI-8582协议芯片和多路开关相互配合构成可动态配置的多收/发通道,简化了硬件电路复杂度;使用混合冗余和大电流保护技术提高了通信可靠性,同时开发了基于VxWorks的板卡驱动.在某飞机配电地面系统中的测试结果表明,该板卡能够实现ARINC429总线系统的相关功能,运行稳定、波形良好,有一定的推广意义.     

A 5–10 GHz SiGe BiCMOS FPGA with new configurable logic block

This paper presents a new multiplexer based FPGA, which can operate at a clock frequency of 5–10 GHz. Redundant switches on the original signal paths are removed improving the performance. The configurable logic blocks (CLBs) power is greatly reduced by using a revised multiplexer structure and turning off unused cells dynamically. More routing capabilities are provided with more inputs/outputs in each direction than similar designs. A chip consisting of four FPGA ring oscillators was fabricated. The Spice simulation results and chip measurements are presented.     

MicroBlaze软核处理器的SPI控制器设计

设计了一种基于Xilinx公司提供的MicroBlaze微处理器的SPI控制器.该SPI具有可配置的分频器、三线—四线转换功能,同时可以根据外接的芯片SPI总线需求配置其数据发送的方式.该SPI控制器的逻辑功能在Modelsim下仿真结果正确,并且在Virtex-7芯片上运用此控制器配置多款高速数据转换器、时钟芯片等.验证结果表明,该SPI控制器具有使用灵活、便于移植、易于使用、可以同时配置多片器件等优点.     

可调可重构的环形振荡器物理不可克隆函数

针对环形振荡器物理不可克隆函数均匀性与独特性不够理想的问题,提出一种可调可重构的环形振荡器物理不可克隆函数设计.该设计包含可重构环形振荡器模块、整合器模块和裁决器模块.可重构环形振荡器模块由多个独立且具有相同设计的可重构环形振荡器-计数器组构成,芯片各部分的工艺偏差由计数器的数值反映;整合器模块通过将多个计数器数值进行...