Novel ultrahigh-density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

In order to overcome the limitation of cell area of 4F/sup 2/ per bit in conventional NAND flash memory cells, stacked-surrounding gate transistor (S-SGT) structured cell is proposed. This newly structured cell achieves a cell area of 4F/sup 2//N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multibit per memory cell technology. The S-SGT structured cell consisting of two stacked memory cells in one silicon pillar achieves a cell area per bit of less than 50% of the smallest reported NAND structured cell. The novel S-SGT structured cells are fabricated by vertical self-aligned processes using a 0.2 /spl mu/m design rule. The S-SGT structured cell can be programmed and erased by uniform injection and uniform emission of Fowler-Nordheim (F-N) tunneling electrons over the whole channel area of the memory cell, respectively, which is the same program and erase mechanism as in conventional NAND structured cell. This high performance S-SGT structured cell is applicable to high-density nonvolatile memories for 16 G/64 G bit Flash memories and beyond.     

A multigigabit DRAM technology with 6F2 open-bitlinecell, distributed overdriven sensing, and stacked-flash fuse

A multigigabit DRAM technology was developed that features a low-noise 6F² open-bitline cell with fully utilized edge arrays, distributed overdriven sensing for operation below 1 V, and a highly reliable post-packaging repair scheme using a stacked-flash fuse. This technology, which can be used to fabricate a 0,13-μm 180-mm² 1-Gb DRAM assembled in a 400-mil package, was verified using a 57.6-mm², 200-MHz array-cycle, 256-Mb test chip with 0.109-μm² cells     

A robust 8F2 ferroelectric RAM cell with depletiondevice (DeFeRAM)

This paper describes an area-penalty-free, leakage-compensated, and noise-immune 8F² cell design suitable for high-density, low-power ferroelectric RAM (FeRAM) generations. The new concept features a 1T1C ferroelectric memory cell containing an additional depletion device (DeFeRAM) controlled by the passing word line in a folded bit-line architecture. The depletion device permits the use of a common cell plate at intermediate voltage level. A highly reliable three-level word-line driver circuit design is discussed     

F+离子注入BaF2薄膜的光学性质

本文报导了F+离子注入对BaF2薄膜的光学性质的影响,实验观察到了离子注入引起的薄膜的透过率谱的变化,在一定温度下退火可以使这种变化消除。     

A new DRAM cell with a transistor on a lateral epitaxial siliconlayer (TOLE cell)

A new dynamic RAM (DRAM) cell structure and its fabrication technology are proposed. The proposed DRAM cell consists of a transistor on a lateral epitaxial silicon layer (TOLE) and a stacked capacitor formed in a trench. It can achieve high immunity to alpha-particle-induced noise and a low parasitic bit-line capacitance. The TOLE structure is produced by a silicon-on-insulator fabrication technology newly developed by combining epitaxial lateral overgrowth and preferential polishing. Reasonable electrical characteristics for the TOLE and high immunity against alpha-particle disturbance for the TOLE cell were confirmed     

A low-noise folded bit-line sensing architecture for multigigabitDRAM with ultrahigh-density 6F2 cell [CMOS design]

The 6F² cell is widely known for its small area, but its sensing is unstable due to the large array noise. A new low-noise sensing scheme for a 6F² DRAM cell is proposed, employing two noise reduction methods: the divided sense and combined restore scheme and the bit-line noise absorbing scheme. They can reduce word-line to bit-line as well as bit-line to bit-line coupling noises. The bit-line noise is reduced to 85% of that of a conventional scheme with only 0.05% area overhead, which is negligible compared to the area saving by using a 6F² cell. The total chip area and the sensing time can he reduced to 85 and 87%, respectively, compared to conventional DRAM. A 2 kbit DRAM test chip with a 6F² cell Is fabricated using 256 M DRAM technology, and its stable operations are confirmed     

Bipolar transistor selected P-channel flash memory cell technology

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory     

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ

This paper describes a 256 Mb DRAM chip architecture which provides up to ×32 wide organization. In order to minimize the die size, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25 μm CMOS technology. The chip measures 13.25 mm×21.55 mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85°C. In addition, a 100 MHz×32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output (EDO) cycle has been successfully demonstrated     

掺硫NaCl晶体中（F_2~＋）_H心的形成及其稳定性

报道了掺硫ＮａＣｌ晶体（Ｆ＿２￣＋）＿Ｈ心的制备过程以及（Ｆ＿２￣＋）＿Ｈ心的室温避光稳定性。讨论了Ｓ２－对Ｆ＿２￣＋的稳定作用和（Ｐ＿２￣＋）Ｈ制备过程中的缺陷化学反应．研究表明．促使Ｆ３心热分解成Ｆ心和控制好转型光的辐照剂量是制备高浓度、高纯度（Ｆ＿２￣＋）＿Ｈ心材料的关键技术之一。     

Ferroelectric DRAM (FEDRAM) FET with metal/SrBi2Ta2O9/SiN/Si gate structure

N-channel ferroelectric dynamic random access memory (FEDRAM) FETs with SrBi₂Ta₂O₉/SiN/Si structure were fabricated and characterized. The estimated switching time (t_sw ) of the fabricated FET, measured at applied electric field of 376 kV/cm, was less than 50 ns, which could be significantly reduced upon scaling. Its remnant polarization (2P_r) was measured to be about 1.5 μC/cm², which is more than one order of magnitude higher than that required for FEDRAM operation. The stored information retains more than three orders of magnitude of on/off ratio up to three days at room temperature, with little fatigue after 10¹¹ switching cycles     

A 7F2 cell and bitline architecture featuring tiltedarray devices and penalty-free vertical BL twists for 4-Gb DRAMs

A 7F² DRAM trench cell and corresponding vertically folded bitline (BL) architecture has been fabricated using a 0.175 μm technology. This concept features an advanced 30° tilted array device layout and an area penalty-free inter-BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals. A significant improvement of signal margin was measured on a 32-Mbyte test chip     

MBE grown n+-i-δ(p+)-i-n+GaAs V-groove barrier transistor

The three-terminal n⁺-i-δ(p⁺)-i-n⁺V-groove barrier transistor (VBT) has been successfully fabricated by molecular beam epitaxy (MBE). The base terminal is connected to the δ(p⁺), the thin p⁺layer, by depositing aluminum on the etched V-groove. The demonstrated device possesses high potential of ultra-high-frequency (f_{r} > 30-GHz), high-power, and low-noise capability due to carriers transporting by thermionic emission and being controlled by the base-emitter bias.     

NaCl：OH~－晶体生长及（F_2~＋）_H心制备

报道了低非激活损耗ＮａＣｌ：ＯＨ－晶体生长及高浓度（Ｆ２＋）Ｈ心的制备并和法国同种晶体进行了比较。     

A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NORtype four-level cell

In order to realize high-capacity and low-cost flash memory, we have developed a 64-Mb flash memory with multilevel cell operation scheme. The 64-Mb flash memory has been achieved in a 98 mm² die size by using four-level per cell operation scheme, NOR type cell array, and 0.4-μm CMOS technology. Using an FN type program/erase cell allows a single 3.3 V supply voltage. In order to establish fast programming operation using Fowler-Nordheim (FN)-NOR type memory cell, we have developed a highly parallel multilevel programming technology. The drain voltage controlled multilevel programming (DCMP) scheme, the parallel multilevel verify (PMV) circuit, and the compact multilevel sense-amplifier (CMS) have been implemented to achieve 128 b parallel programming and 6.3 μs/Byte programming speed     

室温脉冲可调谐NaCl：（F_2~＋）H色心激光器

报道了室温下掺硫及掺氧ＮａＣｌ晶体中（Ｆ_２~＋）Ｈ心的热光稳定性和激光性能。讨论了引起色心退色的原因和改进方法。     

NaCl(OH-):(F2+)H色心激光的研究

文中报道了低温红外连续NaCl(OH-):(F2+)H色心激光的研究结果。当泵浦功率为4.5W,辅助光功率为34.5mW时,输出功率大于250mW,峰值波长为1.57μm。为保证色心激光稳定运转,必须要有辅助光。     

CW laser operation with new F+2-type color centers in NaF

In NaF doped with divalent alkaline earth impurities, thermally stabilized F+2* centers were found. Compared to the corresponding centers in transition-metal-doped crystals, they show improved properties (slope efficiency, output power, reduced fading) as active media in CW color center lasers.     

Characterization of Ge2Sb2Te5 thin film transistor and its application in non-volatile memory

With the increasing requirement of high density memory technology, a new cell structure—1TR has received much attention. It consists of a single thin film transistor (TFT) with chalcogenide Ge₂Sb₂Te₅ as the channel material. In order to evaluate the feasibility of its application in the field of non-volatile memory, we take a further step in researching on the characteristics of GST-TFT. We fabricated a back-gate GST-TFT and investigated the output and transfer characteristics of its two states. The experimental results show that gate voltage can modulate the GST channel currents in both the amorphous and the crystalline states. Based on the experiments, we can expect that this novel device can ultimately lead to a new nonvolatile memory technology with even higher storage density.     

A 76-mm2 8-Mb chain ferroelectric memory

This paper demonstrates the first 8-Mb chain ferroelectric RAM (chain FeRAM) with 0,25-μm 2-metal CMOS technology. A small die of 76 mm² and a high average cell/chip area efficiency of 57.4 % have been realized by introducing not only chain architecture but also four new techniques: 1) a one-pitch shift cell realizes small cell size of 5.2 μm²; 2) a new hierarchical wordline architecture reduces row-decoder and plate-driver areas without an extra metal layer; 3) a small-area dummy cell scheme reduces dummy capacitor size to 1/3 of the conventional one; and 4) a new array activation scheme reduces dataline and second amplifier areas. As a result, the chain architecture with these new techniques reduces die size to 65% of that of the conventional FeRAM. Moreover a ferroelectric capacitor overdrive scheme enables sufficient polarization switching, without overbias memory cell array. This scheme lowers the minimum operation voltage by 0.23 V, and enables 2.5-V V_dd operation. Thanks to fast cell plateline drive of chain architecture, the 8-Mb chain FeRAM has achieved the fastest random access time, 40 ns, and read/write cycle time, 70 ns, at 3.0 V so far reported     

Novel cell transistor using retractedSi3N4-liner STI for the improvement of dataretention time in gigabit density DRAM and beyond

In this paper, we propose a novel cell transistor using retracted Si₃N₄-liner STI (shallow trench isolation) for the enhanced and reliable operation of 256-Mb dynamic random access memory (DRAM) in 0.15-μm technology. As the technology of DRAM has been developed into the sub-quarter-micron regime, the control of junction leakage current at the storage node is much more important due to the increased channel doping concentration. With the decreased parasitic electric field at the STI corner using the retracted Si₃N₄-liner, the inverse narrow width effect (INWE) was significantly reduced. The channel doping concentration, hence, was lowered without degrading the subthreshold leakage characteristics and the channel doping profile was optimized from the viewpoint of the electric field at local areas in the depletion region. In addition to the optimized channel doping profile resulted in a dramatic increase in data retention time and device yield for 256-Mb DRAM. The proposed cell transistor can be extended to future high-density DRAMs in 0.13-μm technology and beyond