A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.     

Single damascene integration of porous Zirkon™ version 1 low-k dielectric films

Zirkon™ LK2000 version 1 dielectric film (Zirkon™ is a trademark of Shipley Company L.L.C), a porous methylsilsesquioxane (MSQ)-based spin-on dielectric with a k value targeted at 2.0, has been integrated in single damascene structures. For patterning, a dual SiC/SiO₂ CVD hard-mask was used. Surface treatments (DUV ozone (DUV-O₃), plasma treatments) were tested to solve the adhesion issues encountered at the CVD hard-mask and the low-k interface. Adhesion is only improved when plasma treatments are used. Analyses (FTIR, TDS, nano-indentation) show that the plasma treatments only modify the low-k surface. For integration, a plasma treatment (He, NH₃, N₂/O₂) prior to deposition of the CVD hard-mask was included. After patterning, copper metallization and CMP of the wafers, electrical evaluation shows that, compared to the reference wafer (no plasma treatment), plasma-treated wafers have a higher yield and a lower sheet resistance. The RC delay is slightly higher for the plasma-treated wafers than for the reference wafer.     

Overview of dual damascene integration schemes in Cu BEOL integration

An overview of different dual damascene approaches is given. Three approaches - trench first, trench first with metal hardmask, and via first - are described in detail. Trench first is the easiest approach but due to its limitation only suitable for wide ground rules with moderate aspect ratios. Via first is capable to run fine pitches and/or higher aspect ratios but has many problems to reach a proper transition between trench and via. With respect to this transition the trench first with metal hardmask concept seems to be advantageous, but it has its own challenges and problems. This article describes our solutions to these problems.     

A copper-dielectric cap interface with high resistance to electromigration for high performance semiconductor devices

In highly integrated semiconductor devices the time to failure of copper interconnects strongly depends on the properties of the copper-dielectric cap interface. In this work a production capable preparation of copper-dielectric cap interfaces with a high resistance to electromigration (EM) has been developed for 90 and 65 nm dual damascene technologies. With a new soft silicidation pretreatment of the copper metallization followed by a deposition of a SiCN or SiN cap the EM lifetime could be improved 3.5× referring to a standard SiCN capping process. The new pretreatment enables the formation of an epitaxial copper silicide layer on top of the copper metal lines which is seen as the key factor of the lifetime improvement. The new kind of cap layer process enables the lifetime improvement with only negligible increase of metal sheet resistance. The surface damage of copper and the low k inter-level dielectric which is typically caused during the copper precleaning could be minimized significantly. It is shown that there is no linear correlation between adhesion to copper and electromigration performance.     

Copper-dielectric cap interface with enhanced reliability for 45 nm technology and beyond

A production capable preparation of a Cu-dielectric cap interface with a significantly enhanced reliability robustness has been developed for the 45 nm dual damascene technology and beyond. The electromigration (EM) lifetime could be improved by a factor of 2 with an advanced in situ cleaning process (ACP) including a soft silicidation step of the Cu metallization prior to the Cu-cap deposition. The increase of the Cu metal line resistivity can be controlled and limited to <6%. Anneal experiments at high temperature underline a high thermal stability of the Cu-cap interface including the copper-silicide (CuSi) intralayer. The new ACP is applicable to Cu interconnects built with dense or porous ultra-low-k (ULK) dielectrics because the process minimizes the surface damage. This yields in a doubled dielectric breakdown strength of a Cu damascene structure with a ULK inter-level dielectric by implementation of the ACP.     

Single mask dual damascene processes

Single mask dual damascene processes are described. The unique mask merges via and modified trench patterns. We design the mask’s trench area to have partial transmission using thin chromium or add phase shifted gratings in the trench area to achieve destructive interference for lowering the intensity. Optical proximity correction is used to obtain the desired lithography process window. Upon exposure, the trench results in a partial exposure while the via is fully exposed and a dual damascene (DD) photoresist profile is created within specifications. Following with an integrated etch can complete the DD image transfer into the underneath dielectric. A single mask DD process eliminates via/trench misalignment issues, can save up to one half of metal mask cost, and 50% of other processing costs. It is expected to also boost yield and improve product reliability.     

以非晶硅为硬掩膜的TaN金属栅的选择性湿法腐蚀

提出了一种在HfSiON介质上,采用非晶硅为硬掩膜的选择性去除TaN的湿法腐蚀工艺。由于SC1(NH4OH:H2O2:H2O)对金属栅具有合适的腐蚀速率且对硬掩膜和高K材料的选择比很高,所以选择它作为TaN的腐蚀溶液。与光刻胶掩膜和TEOS硬掩膜相比,因非晶硅硬掩膜不受SC1溶液的影响且很容易用NH4OH溶液去除（NH4OH溶液对TaN和HfSiON薄膜无损伤）,所以对于在HfSiON介质上实现TaN的选择性去除来说非晶硅硬掩膜是更好的选择。另外,在TaN金属栅湿法腐蚀和硬掩膜去除后, 高K介质的表面是光滑的,这可防止器件性能退化。因此,采用非晶硅为硬掩膜的TaN湿法腐蚀工艺可以应用于双金属栅集成,实现先淀积的TaN金属栅的选择性去除。     

Stabilization of sheet resistance for metal lines by formation of etch stop layer (ESL) trench structure

Sheet resistance of metal lines is mainly affected by critical dimension (CD), etch depth, and chemical mechanical planarization amount in damascene process. Therefore, these factors must be stably controlled in order to stabilize the sheet resistance of metal lines. Especially the etch depth, which is sensitive to the pattern density and the equipment conditions bring not only the variation of sheet resistance of metal lines but also the connection problem to the under-layered contacts. The objective of this study is to reduce the variation of the sheet resistance of metal lines by stabilization of the etch depth with etch stop layer (ESL). SiN film was used as an ESL while the intermetal dielectric (IMD) films were employed by the conventional fluorine-doped silicate glass (FSG)/SiH₄ film with an increment of thickness by the employment of SiN film as an ESL. The selectivity of oxide-to-nitride was about 6.4:1 for etch stop step. While the stop layers were removed after the etch stop step, the pre-metal dielectric was also etched at the same time for the stable connection to the under-layered contacts. Comparing the ESL method to the conventional method, more stable metal lines were formed with the in-line CD measurement, thickness measurement, cross-sectional scanning electron microscopy analysis, and sheet resistance measurement from the view point of the connection to the under-layered contacts. The stable sheet resistance of metal lines was also obtained with the changes in etch time or thickness.     

Reliability of copper low-k interconnects

For the implementation of copper and low-k materials into a tight pitch damascene interconnect architecture it is important to understand and correctly describe the underlying degradation mechanisms during reliability testing. Based on the understanding solutions can be proposed for avoiding fast degradation. While the physical understanding of electromigration mechanisms is less of a debate, technological challenges towards the fabrication of metal wires/vias able to carry the ever increasing current densities are enormous. Recently a number of novel metallization schemes including ruthenium and its alloys or self-forming barriers were proposed. As a consequence, some of the thermodynamic and kinetic behavior of the system can be modified when compared to the conventional Ta-based metallization. Another important component of the system is the insulating low-k dielectric. When scaling the critical dimensions into 50 nm ½ pitch and beyond, the impact of layout and line edge roughness becomes important. If a double patterning approach is used for printing a tight metal pitch, then misalignment between the different photos will exacerbate the layout induced effects. The choice of dielectric material, test structure design and damascene process steps will contribute on top of these effects. Based on recent understanding we review some aspects of novel metallization schemes and tight pitch copper/low-k interconnects from a reliability standpoint.     

Impact of LKD5109™ low-k to cap/liner interfaces in single damascene process and performance

The importance of interface quality in the single damascene integration process of LKD5109™ porous low-k films is investigated. A strong correlation is observed between chemical mechanical planarization (CMP) performance and LKD/cap layer interfacial fracture energies. The use of FF02™ as cap layer material (an on-purpose developed spin-on organic hard-mask) on LKD leads to superior interfacial adhesion and metal continuity yield as compared to the use of chemical vapour deposition SiC:H cap films. The adhesion quality of LKD/liner films appears less critical than LKD/cap layer adhesion as far as CMP performance is concerned. Electrical line-to-line performance is not always directly correlated with adhesion but rather, more generally speaking, with interface quality (i.e., presence of defects/dangling bonds or moisture). The introduction of surface pre-treatments to enhance interfacial adhesion leads to degradation in both leakage current and breakdown field behaviour because of damage induced at the interface.     

Integrating thick copper/Black Diamond™ layer in CMOS interconnect process for RF passive components

Thick copper (Cu)/Black Diamond™ (BD) layer up to 4 μm has successfully been integrated in CMOS interconnect process to improve the quality of on-chip RF passive components. It is shown that BD film is easy to crack when its thickness is up to 4 μm. However, by inserting one or few layers of dielectric material, BloK™, the stress in the entire dielectric film stack can be reduced. Although the reduction of the tensile stress of the stack is insignificant, the inserted BloK™ layer effectively prevents cracking from happening in the film stack. Spiral inductors have been integrated in developed Cu/BD (4 μm) top-metal-layer. Both Q value and resonate frequency of developed inductors are improved comparing to the inductors fabricated in previous top-metal-layer with 1 μm Cu/SiO₂ stack.     

Reactive ion etching and characterization of p-silk ultra low-k film

Reactive ion etch (RIE) of p-SiLK, a spin-on polymer based ultra low-k (ULK) material with a k value of /spl sim/2.2 was characterized and its influence on electrical yield and dielectric breakdown is presented here. Material characterization was done using blanket films after curing and the effect of exposure to different conventional plasma etch gas mixtures was studied for surface composition, roughness and dielectric constant. Trench etch process was developed for 130-nm technology node for single damascene process integration. Dual hard mask approach was taken and two etch schemes viz., etching under hardmask and etching under photoresist were evaluated. In both schemes, trench etch profiles were near vertical and critical dimension (CD) control was within 10%. RIE lag and the carbon depletion at the sidewalls were found to be insignificant confirming acceptable etch process performance. Etching under photoresist scheme was found advantageous in terms of trench profile for isolated structures, reduced cycle time making the process cost effective and reduced post-CMP defects. However, from the comparison of electrical test results, etch under hardmask scheme showed higher electrical yield and better performance than etch under PR scheme. Although trench sidewalls were exposed to plasma during both schemes, sidewall damage did not contribute to overall leakage. The RIE process developed and the characterization results have confirmed the compatibility of material and RIE process for successful process integration.     

Process improvement of 0.13 μm Cu/Low K (Black Diamond) dual damascene interconnection

Once fab develops a reliable integration scheme, the next step of process improvement and yield enhancement is very important for semiconductor industry, especially for the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection. In this paper, we discuss the process integration issues of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene integration. Solutions to the issues were explored and reported. Resist poisoning issue was solved by modifying photoresist and planarizing bottom-anti-reflective-coating (BARC) scheme. As a result there is an increase of 20% electrical yield. The impact of via etch time on interface of via bottom was studied and etch time was optimized for the best electrical performance of via chains. One of major targets of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene integration is the reliability improvement. It was observed that Cu cap etch results in different via chain profiles. Good profile of via chain is achieved after optimizing of Cu cap etch and via etch. The failure open rate of via chain and the highest dielectric breakdown field were also reported. The impacts of dual damascene cleaning on the reliability of the 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection was studied with splits between batch process and single wafer cleaning. On the whole, we successfully integrated 0.13 μm Cu/Low K (Black Diamond^TM) dual damascene interconnection with good electrical and reliability performance after process improvement of patterning, via/Cu cap etch and dual damascene cleaning.     

Selective wet etch of a TaN metal gate with an amorphous-silicon hard mask

The appropriate wet etch process for the selective removal of TaN on the HfSiON dielectric with an amorphous-silicon(a-Si) hardmask is presented.SCI(NH_4OH:H_2O_2:H_2O),which can achieve reasonable etch rates for metal gates and very high selectivity to high-k dielectrics and hardmask materials,is chosen as the TaN etchant. Compared with the photoresist mask and the tetraethyl orthosilicate(TEOS) hardmask,the a-Si hardmask is a better choice to achieve selective removal of TaN on the HfSiON dielectric be...     

Leakage mechanism in Cu damascene structure with methylsilane-dopedlow-K CVD oxide as intermetal dielectric

This letter investigates the leakage mechanism in the Cu damascene structure with methylsilane-doped low-k CVD organosilicate glass (OSG) as the intermetal dielectric (IMD). The leakage between Cu lines was found to be dominated by the Frenkel-Poole (F-P) emission in OSG for the structure using a 50-nm SiC etching stop layer (ESL). In the structure using a 50-nm SiN ESL, the leakage component through SiN also made a considerable contribution to the total leakage in addition to the bulk leakage from trapped electrons in OSG. An appropriate ESL of sufficient thickness is essential to reduce the leakage for application to a Cu damascene integration scheme     

Sub‐Micrometer Zeolite Films on Gold‐Coated Silicon Wafers with Single‐Crystal‐Like Dielectric Constant and Elastic Modulus

A low‐temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low‐k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b‐oriented film of the pure‐silica zeolite MFI (silicalite‐1) supported on a gold‐coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in‐plane growth. The traditional calcination process is replaced with a nonthermal photochemical activation to ensure preservation of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal–insulator–metal configuration, highlights the ultralow k ≈ 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E ≈ 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.     

32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k = 2.3

A 32 nm node BEOL integration scheme is presented with 100 nm metal pitch at local and intermediate levels and 50 nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32 nm RC performance specifications, extreme low-k (ELK) porous SiOCH k = 2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k = 2.3 is investigated using a multi-level metallization test vehicle in a 45 nm mature generation.     

Process damage-free damascene metal gate technology for gentle integration of epitaxially grown high-k

This paper presents the first successful attempt to integrate crystalline high-k gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness (EOT) down to 1.9 nm are discussed and compared with devices with rare-earth gate dielectrics fabricated previously in a conventional CMOS process.     

Investigation of defect on copper bond pad surface in copper/low k process integration

In this work, inspection tools and surface analysis instruments were used to inspect and to analyze the defects at copper bond pads fabricated with copper/low k dual damascene deep submicron interconnect process integration. The defects at level are believed to be responsible for metal peeling at the Ta + Al and copper interface observed during chip wire bonding operation. The analysis results of the trace defects’ chemical composition show that the trace defects are the remainder of dielectric materials of passivation layer that is deposited on the top of the chip for protection. Copper oxide is also found to be present at the copper bond pads surface. A clear copper bond pad surface could be obtained using optimized dielectric pad window opening plasma etching conditions with suitable level plasma etching power and some overetch, improved photoresist stripping with oxygen and wet clean recipe with some chemicals. A clear copper bond pad surface will contribute to obtainment higher adhesion and lower contact resistance at Ta + Al and copper pad interface.     

Reliability studies of barrier layers for Cu/PAE low-k interconnects

Electromigration and electrical breakdown are two of the most important concerns in the reliability of modern electronic devices. The electromigration lifetimes and electrical breakdown field (E_BD) in single damascene copper lines/porous polyarylene ether (PAE) dielectric with different diffusion barrier materials (i.e., amorphous-SiC:H and TaN/Ta) were studied. The results showed a “wafer edge effect” in both groups of samples. The electromigration lifetime of samples taken from the center of the wafer is five to nine times longer of those taken from the wafer edge in the accelerated test. The samples from wafer edge showed a bi-modal failure characteristic. It was also found that electromigration resistance of the structure with new diffusion barrier a-SiC:H/Ta was comparable to that with the conventional TaN/Ta. On the other hand, the electrical testing showed that E_BD of the a-SiC:H/Ta structure is about twice of that with TaN/Ta barrier, indicating a significant improvement of the electrical performance.