软硬件协同设计中的软硬件划分方法综述

近年来,随着信息领域的物联网、工业互联网、机器人等研究热点发展,嵌入式系统技术再次得到科技工作者和工程师的广泛关注和重视,同时嵌入式系统产品的集成度和性能要求越来越高.软硬件协同设计是开发嵌入式系统产品的重要方法之一,而软硬件划分是软硬件协同设计中的关键技术.本文对现有软硬件划分方法从不同层面进行梳理和分类,重点介绍几种常用的软硬件划分方法,并结合实例进行了详细阐述,最后对这几种方法进行综合比较,供嵌入式系统开发科技工作者和工程师参考.     

基于SystemC的嵌入式系统软硬件协同设计

提出了一种基于SystemC的嵌入式系统软硬件协同设计方法。SystemC是OSCI(OpenSystemCIni tiative)组织制定和维护的一种开放源代码的C 建模平台 ,提供支持硬件建模和仿真的C 类库及相应的仿真内核。通过SystemC的支持 ,该方法在整个嵌入式系统设计流程内使用C 语言来统一描述硬件和软件 ,实现软硬件的协同设计和仿真。该方法同传统的设计方法相比更加灵活和有效。     

基于UML的软硬件协同设计方法

嵌入式系统软硬件协同设计中关键步骤之一是软硬件划分。文中通过介绍现有嵌入式系统的协同设计方法，如：VULCAN，COSYMA和POLLS，指出了现有方法的缺点，提出了一种改进的基于UML的新方法。使用UML建立系统模型，根据UML的图例，采用二叉树的结构，计算出每个步骤的成本；采用改进的遗传算法，加快收敛的速度，提高解的质量。在算法库和成本库中对系统的软硬件进行划分，通过协同综合，达到协同仿真和验证的目的。     

实现SOPC的嵌入式软硬件协同设计平台

对基于FPGA的SOPC软硬件协同设计方法进行了研究,在此基础上,详细设计了系统硬件平台,并对硬件平台的硬件系统进行了定制.本平台满足了从硬件系统定制,到操作系统配置均可以按照设计需求进行定制的特点.     

嵌入式系统软硬件协同设计中的快速样机平台

提出一种嵌入式系统软硬件协同设计的快速样机平台设计方案，该方案使用系统级可编程芯片和处理机软核技术来构成快速样机平台所需的FPGA阵列和规模可调的处理机，以此实现软硬件的更紧密灵活的耦合和更小的通信延迟．可重构逻辑的应用使得该快速样机平台具有简单规整的结构，一方面使得快速样机平台之间的扩展连接更为容易，另一方面使得FPGA芯片中的逻辑资源能得到更充分利用．     

基于UML的软硬件协同设计方法

嵌入式系统软硬件协同设计中关键步骤之一是软硬件划分。文中通过介绍现有嵌入式系统的协同设计方法,如:VULCAN,COSYMA和POLIS,指出了现有方法的缺点,提出了一种改进的基于UML的新方法。使用UML建立系统模型,根据UML的图例,采用二叉树的结构,计算出每个步骤的成本;采用改进的遗传算法,加快收敛的速度,提高解的质量。在算法库和成本库中对系统的软硬件进行划分,通过协同综合,达到协同仿真和验证的目的。     

软硬件协同设计算法的嵌入式人脸识别系统

研究人脸识别系统的软硬件设计优化问题,软硬件协同设计是一个多约束条件、多目标的组合优化问题,单一方法难以找到最优协同设计方案.为此,提出一种采用遗传-蚁群算法的嵌入式人脸识别系统软硬件协同设计方法.首先建立软硬件协同设计问题的数学模型,然后利用遗传算法找到问题的可行解,最后采用蚁群算法在可行解中找到全局最优协同设计方案.仿真结果表明,遗传-蚁群算法很好的利用了两种算法优势,解决了单一算法存在局部极优、早熟等难题,提高了软硬件协同设计方案的求解效率,可以找到更优的嵌入式人脸识别系统软硬件协同设计方案.     

SoPC与嵌入式系统软硬件协同设计

软硬件协同设计是电子系统复杂化后的一种设计新趋势,其中SoC和SoPC是这一趋势的典型代表。SoPC技术为系统芯片设计提供了一种更为方便?灵活和可靠的实现方式。在介绍系统级芯片设计技术的发展由来后,重点介绍SoPC设计系统芯片中的软硬件协同设计方法,并指出它比SoC实现方式所具有的优势。     

一种基于SystemC的系统级软硬件协同设计新模型

分析了SystemC的建模特性,提出了一种基于SystemC的系统级设计新模型,即从系统功能描述开始逐步细化,建立模型间通信抽象的事务模型,对抽象通信具体化,最后形成通信模型。以此为基础进行RTL级综合,完成软硬件协同设计。本方法应用于一款导航芯片的设计,有效地缩短了研制周期,降低了开发成本,提高了系统设计质量。     

软硬件协同设计环境中性能分析工具的研究与实现

软硬件协同设计中的性能分析常常使设计者将过多的精力用于对大量数据的整理和分析,从而降低了设计效率。集成的软硬件协同设计环境iCDMdt中的性能分析工具以验证平台采集的分析数据和用户设置为输入,在同一环境下以内嵌的分析图形输出,用简捷明了的方式帮助设计者实现性能分析。本文对iCDMdt环境中性能分析工具及其实现进行了详细叙述,并以普通电话机模型作为集成的软硬件协同设计环境iCDMdt的设计实例应用其性能分析工具。     

Acceleration of software algorithms using hardware/software co-design techniques

Currently there is significant interest in the design and implementation of embedded systems where the hardware and software subsystems are developed concurrently in order to meet design constraints. We present a development environment for general-purpose systems, where the objective is to accelerate the performance of software-based applications, which are specified by C programs. Such programs may be partitioned into hardware and software subsystems — a speed-critical region of the software is implemented in an FPGA in order to provide the performance acceleration. We also discuss two versions of the underlying system hardware architecture. Practical examples are given to illustrate our approach.     

嵌入式系统软硬件划分方法探索

提出了克隆选择算法在软硬件划分中的应用,讨论了目标函数、系统约束、抗体编码、克隆选择和变异等问题的处理。实验结果表明该算法具有较快的收敛速度,并获得了近似最优解。     

An Algebraic Hardware/Software Partitioning Algorithm

Hardware and software co-design is a design technique which delivers computer systems comprising hardware and software components.A critical phase of the co-design process is to decompose a program into hardware and software .This paper proposes an algebraic partitioning algorithm whose correctness is verified in program algebra.The authors inroduce a program analysis phase before program partitioning and deveop a collection of syntax-based splitting rules.The former provides the information for moving operations from software to hardware and reducing the interaction between compoents,and th latter supports a compositional approach to program partitioning.     

基于软硬件协同的AFDX协议片上系统设计

在描述片上系统总体结构的基础上,详细介绍了硬件功能、软件功能及软硬件之间的接口,重点论述了基于同步调度或异步调度的调度器设计方案、基于Mealy有限状态机的虚拟链传输控制等关键技术。在EP1S40芯片上经过验证可满足航空电子全双工交换式以太网(AFDX)协议处理芯片的设计要求。     

Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms

In this contribution we present a new paradigm and methodology for the Network-on-chip (NoC) based design of complex hardware/software systems. While classical industrial design platforms represent dedicated fixed architectures for specific applications, flexible NoC architectures open new degrees of system reconfigurability. After giving an overview on required demands for NoC hyper-platforms, we describe the realisation of these prerequisites within the HiNoC platform. We introduce a new dynamic hardware/software co-design methodology for pre- and post-manufacturing design. Finally we will summarize the concept combined with an outlook on further investigations.     

An efficient GPU-based parallel tabu search algorithm for hardware/software co-design

Hardware/software partitioning is an essential step in hardware/software co-design. For large size problems, it is difficult to consider both solution quality and time. This paper presents an efficient GPU-based parallel tabu search algorithm (GPTS) for HW/SW partitioning. A single GPU kernel of compacting neighborhood is proposed to reduce the amount of GPU global memory accesses theoretically. A kernel fusion strategy is further proposed to reduce the amount of GPU global memory accesses of GPTS. To further minimize the transfer overhead of GPTS between CPU and GPU, an optimized transfer strategy for GPU-based tabu evaluation is proposed, which considers that all the candidates do not satisfy the given constraint. Experiments show that GPTS outperforms state-of-the-art work of tabu search and is competitive with other methods for HW/SW partitioning. The proposed parallelization is significant when considering the ordinary GPU platform.     

嵌入式系统软硬件自动划分方法研究

软硬件划分一直是嵌入式系统软硬件协同设计中的难点,如果离开具体系统,单纯的软硬件划分,其性能很难评估。本文提出基于系统体系结构,应用遗传算法来进行多目标优化的软硬件自动划分方法。在具体设计中,使用数据流图对系统建模,采用邻接表进行个体编码,定义交叉、变异操作,同时引入小生境技术,保持解的多样性。该方法为嵌入式系统软硬件自动划分提供一种新思路。     

嵌入式系统软/硬件协同设计技术综述

随着微电子技术和计算机技术的飞速发展,嵌入式产品广泛应用于消费电子、智能家电、通信设备等多个领域。介绍了嵌入式系统现状,分析了今后的发展趋势,阐述了传统方法的缺陷,介绍了一个新的设计方法学——SoC(片上系统)嵌入式系统软/硬件协同设计,并较详细分析了支撑该方法学的相关技术。     

Convex regularization-based hardware/software co-design for real-time enhancement of remote sensing imagery

In this paper, we address a new approach for high-resolution reconstruction and enhancement of remote sensing (RS) imagery in near-real computational time based on the aggregated hardware/software (HW/SW) co-design paradigm. The software design is aimed at the algorithmic-level decrease of the computational load of the large-scale RS image enhancement tasks via incorporating into the fixed-point iterative reconstruction/enhancement procedures the convex convergence enforcement regularization by constructing the proper projectors onto convex sets (POCS) in the solution domain. The established POCS-regularized iterative techniques are performed separately along the range and azimuth directions over the RS scene frame making an optimal use of the sparseness properties of the employed sensor system modulation format. The hardware design is oriented on employing the Xilinx Field Programmable Gate Array XC4VSX35-10ff668 and performing the image enhancement/reconstruction tasks in a computationally efficient parallel fashion that meets the near-real time imaging system requirements. Finally, we report some simulation results and discuss the implementation performance issues related to enhancement of the real-world RS imagery indicative of the significantly increased performance efficiency gained with the developed approach.