对JTIDS的多音扫频干扰的研究

联合战术信息分发系统(JTIDS)采用跳频、直接序列扩频以及信道编码技术,具有很强的抗干扰能力。使用多音干扰时,需要考虑干扰频率与JTIDS载波频率的频率偏差问题,而使用多音扫频干扰时,只需要设定一个扫频带宽,在JTIDS载波频率附近反复扫描干扰此带宽即可。在JTIDS数据链路模型中加入了三种不同扫频方式的多音扫频干扰进行仿真,并与多音干扰进行对比。仿真结果表明,三种多音扫频干扰的误码率明显大于多音干扰。加入多音干扰时,干扰频率与JTIDS载波频率的频率偏差为1.2MHz时的误码率最大,加入多音扫频干扰时,扫频带宽为0.6MHz到0.8MHz时的误码率最大,而且干扰的效果还与扫频方式有关。     

频域差分和时域差分检测OFDM的误码率性能对比

在多径衰落信道条件下,分析了正交频分复用系统的频域差分检测和时域差分检测的误码率性能,得到了两种系统的误码率解析表达式,并进行了仿真验证.分析和仿真的结果表明:在保护时隙长度不小于最大多径时延长度的条件下,时域差分检测的误码率性能不受信道相干带宽变化的影响,时域差分检测的误码率性能主要受到信道相干时间变化的影响;频域差分检测的误码率性能同时受到信道相干时间和相干带宽变化的影响,并且相干带宽对频域差分检测的影响更大.     

TD-SCDMA1.4MHz载波干扰性能分析

本文主要分析了TD-SCDMA 1.4MHz 载波分别与邻近1.4MHz 和1.6MHz 载波共存的干扰性能.通过理论计算,给出了1.4MHz 相对于1.6MHz 带宽时,基站和终端的ACLR 和ACS 射频指标下降程度,并与测试结果进行对比.最后,通过系统级仿真,给出了1.4MHz 和1.6MHz 载波共存时,系统容...     

多径衰落信道下频域差分检测OFDM系统的误码率分析

在多径衰落信道条件下，分析了正交频分复用系统中频域差分检测的误码率性能，并进行了仿真验证。分析与仿真结果表明，信道相干时间和相干带宽均影响频域差分检测的误码率性能，信道相干带宽对频域差分检测的影响比信道相干时间的影响更大，频域差分检测适合于多径延迟扩展比较小的信道。     

星载柔性转发器系统性能分析

基于多相滤波和调制滤波器组的数字信道化技术是实现星上柔性转发的主要方法。由于调制滤波器组使用的原型滤波器不是理想滤波器,不同用户信号间存在功率泄漏,同时柔性转发器对信号进行处理时还会使信号产生微小失真,这些最终都会表现为系统信噪比的损失或误码率的增大。为了研究功率泄露和信号失真对系统性能的影响,分析柔性转发器中调制滤波器组的性能特性,将滤波器组的设计转换为原型滤波器的设计,再针对不同用户带宽下系统的误码率性能进行仿真,最终确定在原型滤波器固定后影响系统性能的主要原因为用户信号的带宽大小。     

LonWorks测试系统的设计

采用模块化结构设计了电力线载波网络性能测试系统,对网络的延时、带宽和误码率进行测试,使用电力线通信分析仪PLCA-22对此电力线载波网络的延时、带宽和误码率进行测试,以验证此性能测试系统设计的正确性.     

一种宽带多模数字抽取滤波器

提出了一种应用于连续时间Σ-Δ ADC的多模数字抽取滤波器。通过采用不同类型滤波器级联结构,合理分配不同级间下采样因子,有效降低了电路复杂度、面积和功耗。通过级间滤波器相互配合,实现了该滤波器的多带宽、多模式功能。基于65 nm CMOS工艺进行后端设计,仿真结果表明,该多模抽取滤波器的工作带宽为20~50 MHz,当工作带宽为20 MHz和50 MHz时,有效位数分别为10.64位和10.48位。     

双选信道下一种基于混沌交织的FBMC系统

高速移动环境下,无线信道具有时频双选性衰落的特性,使得滤波器组多载波(Filter Bank Multi-carrier,FBMC)系统产生长突发差错。将一种基于Baker映射的混沌交织算法应用在滤波器组多载波系统中,根据混沌密钥对发送数据进行分块和重新排列,按照Baker映射规则完成数据交织。此方法可以将长突发差错变为单突发差错,结合卷积编码能有效地纠正双选信道产生的长突发差错。仿真结果表明,在双选择信道中,基于混沌交织的滤波器组多载波系统误比特率性能优于传统基于块交织的滤波器组多载波系统。     

正交多载波降噪差分混沌键控通信系统

为解决多载波差分混沌移位键控(MC-DCSK)系统传输速率低和误码性能差的缺点,该文提出一种正交多载波降噪差分混沌移位键控(QMC-NR-DCSK)系统。在发送端,预定义载波用于发送参考信号,剩余M-1个不同中心频率的载波及其经正交调制技术后得到的频率相同但相位正交的载波都用于传输信息信号,此外,通过进一步引入Hilbert变换,将系统的频带利用率和传输速率提升为MC-DCSK系统的4倍。在接收端引入滑动平均滤波器的降噪操作降低了噪声的方差,从而改善了系统误码性能。推导了QMC-NR-DCSK系统在加性高斯白噪声(AWGN)信道和多径瑞利衰落(RFC)信道下的比特误码率公式并进行了仿真。仿真结果和理论分析表明：QMC-NR-DCSK系统能有效提升传输速率、带宽效率和误码性能,为该系统应用于多载波无线通信提供理论参考。     

动态环境下载波锁相跟踪环的信号级仿真

在接收信号载噪比一定的前提下,针对GPS软件接收机在不同运动状态下载波环跟踪的问题,仿真研究了不同环路的跟踪性能:在低加速度动态下采用2阶锁相环跟踪更佳,在高加速度动态下则应该采用3阶锁相环跟踪。通过仿真验证了环路的有效性。此外通过仿真发现当载噪比和滤波器噪声带宽一定的情况下,选择合适的预检测积分时间可以有利于载波跟踪。     

Jitter performance of a baseband sampled code tracking loop

The purpose of this paper is to investigate the steady-state tracking performance of a digital baseband noncoherent code tracking loop in the presence of additive white Gaussian noise (AWGN). The delay-locked loop (DLL) structure is evaluated. Particular areas of concern are the effect of carrier frequency uncertainty, branch filter bandwidth and loop filter bandwidth. For a fixed data rate, code chip rate and signal-to-noise ratio there is an optimum length for the digital branch filters which minimizes the tracking jitter     

Circuit design and performance analysis of carrier recovery loopfor digital DBS system in the presence of phase noise

The theoretical analysis of a digital satellite broadcasting system in the presence of phase noise is performed. An effective technique to design the carrier recovery circuit is also presented based on the analyzed loop parameters, such as degradation loss due to phase noise, average time to cycle slip, and carrier signal acquisition time. It is possible to design a system providing the optimal service and satisfying service requirements for a digital satellite broadcasting system. In this paper, the carrier recovery loop that provides optimal performance in the presence of phase noise exhibits the parameters of 0.707 for damping factor and 40 kHz for noise bandwidth. The designed phase-locked loop indicates a performance of 0.26 dB for impairment due to phase noise at 10^-3 BER, 3.88×10⁶ hours for average time to cycle slip, and 34 msec for carrier signal acquisition time. The carrier acquisition time of the designed carrier recovery circuit is in accordance with the analyzed result     

零中频DVB/DAB/CMMB调谐器中可编程信道滤波器设计

介绍了应用于多模多频(DVB/DAB/CMMB)移动数字电视接收的可编程信道滤波器设计.滤波器采用0.1dB波纹的7阶切比雪夫(Chebyshev)Ⅰ型低通结构,截止频率1.8/2.5/3/3.5/4 MHz可编程,在偏离截止频率1.25/4 MHz的频点上,分别实现26/57 dB衰减.多级直流负反馈环路用于抵消因版...     

A 2.5-V 56-mW baseband chain in a multistandard TV tuner for mobile and multimedia applications

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm~2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.     

一种AD9371宽带无线同步定时模块简化方法

在满带宽100 MHz条件下,AD9371的收、发采样频偏问题严重,不采用精确的同步定时模块时,在高斯白噪声信道下测试,误码率较调制误差公式erf值偏高.传统的Gardner定时同步算法虽能降低采样频偏,但Gardner算法的实现复杂度太高.针对这对性能和复杂度间的矛盾,给出了一种同步定时模块的现场可编程门阵列(Fie...     

Carrier and Clock Recovery for 8 PSK Synchronous Demodulation

Synchronous demodulation of Phase-shift-keyed transmissions requires the recovery of carrier and clock timing signals. Envelope detection of the 70 MHz IF signal is used to recover clock, and baseband processing is used to recover carrier for an 8 PSK digital radio with a data rate of 90 Mbits/s in the 11 GHz band. A sequential phase detector is used in a high noise application. Two versions of the carrier recovery circuit are presented. The first one employs hot carrier diode quads to form a compound Costas loop. The second one employs ECL exclusive-OR gates. Emphasis is placed on providing high performance while conserving energy, space, and manufacturing cost.     

Optimum Design and Performance of Costas Recievers Containing Soft Bandpass Limiters

This paper investigates several key questions concerning the mechanization and design of a Costas receiver for reconstruction of a carrier from a suppressed carrier signal. For baseband NRZ encoded data symbols and a soft bandpass limiter preceding the loop, several design issues which are considered herein and which affect acquisition and tracking performance are: (1) The choice of an IF bandwidth. (2) The optimum choice of the Costas arm filter bandwidths as well as the spectral roll-off characteristics. (3) The optimum choice of loop bandwidth to data rate ratio for a given signal-to-noise ratio. (4) The signal suppression factor and the combined limiter-squaring loss. (5) The variations in loop bandwidth and damping with signal level. (6) The choice of the limiter transfer characteristic. (7) Performance degradation due to the presence of a limiter. Various new results in system design are presented and typical numerical results are given and graphically demonstrated in SNR regions of practical interest. The theory is applicable to the design of carrier reconstruction loops required in the implementation of spread spectrum communication receivers.     

Reducing the PLL noise bandwidth by a digital split-loop

The advantages of the split-loop technique for analog phase-locked loops with a time delay are well known. In this paper, it will be shown that the digital counterpart of the split-loop offers an additional advantage, since the first oscillator can already convert the incoming signal down into the baseband. If this signal is used for the demodulation, the noise bandwidth of the loop is reduced significantly without changing the acquisition and tracking ranges. The resulting noise bandwidth is calculated and compared to a conventional digital high-gain second-order loop. Furthermore, the effect on the BER performance for DQPSK modulation is simulated     

Adaptive Blocker Rejection Continuous-Time $Sigma Delta $ ADC for Mobile WiMAX Applications

An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (SigmaDelta) analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures the ADC loop architecture to avoid overloading in the presence of strong interferers, improving receiver channel selectivity and sensitivity without increasing its dynamic range (DR) requirements. The adaptive operation relaxes receiver baseband channel filtering requirements for a worldwide inter-operability for microwave access (WiMAX, IEEE 802.16e) receiver. The ADC achieves 71 dB of dynamic range (DR), 65 dB of peak SNDR and 68 dB of peak SNR over a 10 MHz signal bandwidth, consuming 18 mW from a 1.2 V supply. The ADC system reconfigures the loop filter topology within 51 mus, improving receiver selectivity without any transient impact on BER. In the blocker suppression mode, the ADC can withstand 30 dBc blocker at the adjacent channel, achieving - 22 dB error vector magnitude (EVM) with a 24 Mb/s 16-QAM signal. The IC is fabricated on a 130 nm 8-level metal, metal-insulator-metal (MIM) capacitor, CMOS technology, occupying 1.5 times 0.9 mm² silicon area.     

Tracking Performance of Costas Loops with Hard-Limited In-Phase Channel

It is becoming increasingly popular in the design of suppressed carrier receivers, which employ Costas loops for earrier reconstruction, to hard-limit the output of the in-phase channel. Doing so allows replacement of the analog multiplier, which forms the loop error signal, with a chopper-type device which typically exhibits much less dc offset. The false lock behavior of such a hard-limited loop was recently investigated and shown to be quite different from that of the conventional Costas loop without the hard limiter. This paper presents the companion, analysis of the tracking performance of the hard-limited loop and assesses the penalty, if indeed it is a penalty rather than an improvement, in this performance relative to the conventional Costas loop with an analog third multiplier. In particular, for the case ofRCarm filters and NRZ data, the squaring loss (or equivalently the linear loop tracking jitter) is evaluated and illustrated as a function of the ratio of arm filter bandwidth to data rate and data signal-to-noise ratio. Superimposed on these numerical results will be the corresponding ones for the conventional Costas loop. As a finale, the equivalence in operation of the Costas loop with hard-limited in-phase channel and a baseband modulation carrier reconstruction loop referred to as a demod/ remod loop is discussed.