A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOStechnology

This paper describes the design of a CMOS frequency synthesizer targeting wireless local-area network applications in the 5-GHz range. Based on an integer-N architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4-μm digital CMOS technology, the circuit provides a channel spacing of 23.5 MHz at 5.2 GHz while exhibiting a phase noise of -115 dBc/Hz at 2.6 GHz and -100 dBc/Hz at 5.2 GHz (both at 10-MHz offset). The reference sidebands are at -53 dBc at 2.6 GHz, and the power dissipation from a 2.6-V supply is 47 mW     

A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture

A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new low-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-/spl mu/m CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of -55 dBc. The chip's output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm/spl deg/.     

A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider

The adoption of dynamic dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-/spl mu/m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz over the whole tuning range.     

A SiGe BiCMOS 24-GHz receiver front-end for automotive short-range radar

This paper presents a fully integrated SiGe BiCMOS 24-GHz receiver front-end implemented for a ultra-wideband automotive short-range radar sensor. The circuit consists of a homodyne I/Q down-converter and a 24-GHz synthesizer. The receiver front-end is able to achieve a power conversion gain as high as 30 dB and a 6-dB noise figure, while preserving high linearity performance thanks to a 1-bit gain control. The frequency synthesizer, which also includes an on-chip loop filter, guarantees a phase noise of −104 dBc/Hz at 1-MHz offset from the 24.125-GHz carrier and a 4.7-GHz tuning range from 20.4 to 25.1 GHz.     

A spur-reduction technique for a 5-GHz frequency synthesizer

A spur-reduction technique is presented to achieve low reference spurs for a 5-GHz frequency synthesizer. A dual-path control scheme incorporated with a pair of the proposed smoothed varactors reduces the gain of voltage-controlled oscillator to less than 15 MHz/V, attenuates the spurious tones, and shortens the simulated settling time by 56%. In, addition, a digital frequency-calibration circuit is used to enlarge the tuning range to overcome process variations. A 5-GHz frequency synthesizer has been fabricated for verification in a 0.18-/spl mu/m CMOS process. It exhibits phase noise of -79 and -113 dBc/Hz at 10-kHz and 1-MHz offset, respectively. The reference spur level of -74 dBc is achieved by using a second-order loop filter. The overall tuning range is 16.3% and power consumption is 36 mW from a 1.8-V supply. The total switching time including digital frequency calibration takes no more than 110 /spl mu/s.     

A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop

A 1.5-V 5.5-GHz fully integrated phase-locked loop (PLL) has been implemented in a 0.25-μm foundry digital CMOS process. From a 5.5-GHz carrier, the in-band phase noise can be as low as -88 dBc/Hz at a 40-kHz offset, while the phase noise for the free-running VCO is -116 dBc/Hz at an 1-MHz offset. The VCO core current is 4.6 mA. The prescaler is implemented using a variation of the source-coupled logic (SCL) structure to reduce the switching noise, and thus to reduce the PLL side-band spurs. At -18 dBm signal power measured off chip, the switching noise coupled through substrate and metal interconnect generates spurs with power levels less than -99 dBm when the loop is open. A new charge-pump circuit is developed to reduce the current glitch at the output node. By incorporating a voltage doubler, the voltage dynamic range at the charge-pump output and thus the VCO control voltage range is increased from 1.3 to 2.6 V with immeasurable phase noise and spurious level degradation to the PLL. When the loop is closed, the power levels of side-band spurs at the offset frequency equal to the ~43-MHz reference frequency are < -69 dBc. The total power consumption of the PLL including that for the output buffers is ~23 mW     

An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with<10-Hz RF carrier resolution

A 2.5-GHz/900-MHz dual fractional-N/integer-N frequency synthesizer is implemented in 0.35-μm 25-GHz BiCMOS. A ΔΣ fractional-N synthesizer is employed for RF channels to have agile switching, low in-band noise, and fine frequency resolution. Implementing two synthesizers with an on-chip ΔΣ modulator in a small package is challenging since the modulator induces substantial digital noise. In this work, several design aspects regarding noise coupling are considered. The fractional-N synthesizer offers less than 10-Hz frequency resolution having the in-band noise contribution of -88 dBc/Hz for 2.47-GHz output frequency and -98 dBc/Hz for 1.15-GHz output frequency, both measured at 20-kHz offset frequency. The prototype dual synthesizer consumes 18 mW with 2.6-V supply     

一种9.8-mW 1.2-GHz CMOS 低噪声正交输出频率综合器

实现了一种基于标准0.18µm CMOS工艺的应用于北斗导航射频接收机的1.2GHz频率综合器。在频率综合器中采用了一种基于分布式偏置技术实现的低噪声高线性LC压控振荡器和一种基于源极耦合逻辑的高速低开关噪声正交输出二分频器,集成了基于与非触发器结构的高速8/9双模预分频器、无死区效应的延迟可编程的鉴频鉴相器和电流可编程的电荷泵。该频率综合器的输出频率范围从1.05到1.30GHz。当输出频率为1.21GHz 时,在100-kHz和1-MHz的频偏处相位噪声分别为-98.53dBc/Hz和-121.92dBc/Hz。工作电压为1.8V时,不包括输出Buffer的核心电路功耗为9.8mW。北斗射频接收机整体芯片面积为2.41.6 mm2。     

A low-phase-noise voltage-controlled oscillator for 17-GHz applications

A silicon bipolar voltage-controlled oscillator (VCO) for 17-GHz applications is presented. The VCO is composed of a core oscillating at 9GHz followed by a frequency doubler. It adopts a transformer-based topology to obtain both wide tuning range and low noise performance. The VCO exhibits a tuning range of 4.1GHz from 16.4 to 20.5GHz and a phase noise as low as -109dBc/Hz at a 1-MHz frequency offset from a carrier of 18.5GHz.     

A 1.8-GHz self-calibrated phase-locked loop with precise I/Qmatching

This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-μm CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply     

应用于60-GHz无线通信的全差分锁相环频率综合器

A 40-GHz phase-locked loop(PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator(VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector(PFD)and the charge pump(CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 d Bc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.     

A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS

This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.     

A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO

A 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20 kHz loop bandwidth and -118 dBc/Hz at 1 MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 mm/spl times/2.9 mm.     

A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SCtuning loop

A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-μm CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (K_VCO) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply     

An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL

This paper reports an agile VCO frequency calibration technique and its application on a 10-GHz CMOS integer-N phase-locked loop. The proposed calibration method accomplishes efficient search for an optimum VCO discrete tuning curve among a group of frequency sub-bands. The agility is attributed to a proposed frequency comparison technique which is based on measuring the period difference between two signals. Other mixed-signal circuits are also developed to facilitate this approach. The PLL incorporating the proposed calibration technique is implemented in a 0.18-mum CMOS process. The measured PLL phase noise at 10 GHz is -102 dBc/Hz at 1-MHz offset frequency and the reference spurs are lower than -48 dBc. The PLL consumes 44 mW in the low-current mode. The calibration time is less than 4mus     

A 140-GHz fundamental mode voltage-controlled oscillator in 90-nm CMOS technology

Fundamental mode voltage-controlled oscillators in F-band (90-140GHz) were fabricated using the UMC 90-nm logic CMOS process. The maximum operating frequencies of these three oscillators are 110, 123, and 140GHz, respectively. The 140-GHz voltage controlled oscillator provides -22 to -19-dBm output power, a frequency tuning range of 1.2GHz and phase noise of -85dBc/Hz at 2-MHz offset from the carrier, while consuming 8mA from a 1.2-V supply.     

An Integrated 5–2.5-GHz Direct-Injection Locked Quadrature LC VCO

This letter presents an integrated direct-injection locked quadrature voltage controlled oscillator (VCO), consisted of a 5-GHz VCO integrated with injection locked LC frequency dividers for low-power quadrature generation. The circuit is implemented using a standard 0.18-mum CMOS process. The differential VCO is a full PMOS Colpitts oscillator, and the frequency divider is performed by adding an injection nMOS between the differential outputs of complementary cross-coupled np-core LC VCO. The measurement results show that at the supply voltage of 1.8-V, the master 5-GHz VCO is tunable from 4.73 to 5.74GHz, and the slave 2.5-GHz VCO is tunable from 2.36 to 2.87GHz. The measured phase noise of master VCO is -118.2dBc/Hz while the locked quadrature output phase noise is -124.4dBc/Hz at 1-MHz offset frequency, which is 6.2dB lower than the master VCO. The core power consumptions are 7.8 and 8.7mW at master and slave VCOs, respectively     

A 0.8-V 4.9-mW 1.2-GHz CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers

A fully integrated CMOS frequency synthesizer for UHF RFID reader is implemented in a 0.18-$mu$m CMOS technology. Due to the large self-interference and the backscatter scheme of the passive tags, reader synthesizer's phase noise requirement is stringent to minimize the sensitivity degradation of the reader RX. The modified transformer feedback voltage-controlled oscillator (VCO) exhibits enhanced tank impedance and even harmonic noise filtering to achieve low phase noise. A third-order 2-bit single-loop $Sigma Delta$ modulator is optimized for the proposed synthesizer in terms of phase noise and power. The synthesizer provides a frequency resolution of 25-kHz with a tuning range from 1.03 GHz to 1.4 GHz . Phase noise of ${-}$70 dBc/Hz inband, ${-}$104 dBc/Hz at 200-kHz offset and ${-}$ 121 dBc/Hz at 1-MHz offset with a reference spur of ${-}$84 dBc are measured at a center frequency of 1.17 GHz and a loop bandwidth of 35 kHz. Power dissipation is 4.92 mW from a 0.8 V supply.      

A 5-GHz low phase noise differential colpitts CMOS VCO

A low noise 5-GHz differential Colpitts CMOS voltage-controlled oscillator (VCO) is proposed in this letter. The Colpitts VCO core adopts only PMOS in a 0.18-/spl mu/m CMOS technology to achieve a better phase noise performance since PMOS has lower 1/f noise than NMOS. The VCO operates from 4.61 to 5 GHz with 8.3% tuning range. The measured phase noise at 1-MHz offset is -120.42 dBc/Hz at 5 GHz and -120.99 dBc/Hz at 4.61 GHz. The power consumption of the VCO core is only 3 mW. To the authors' knowledge, this differential Colpitts CMOS VCO achieves the best figure of merit (FOM) of 189.6 dB at 5-GHz band.     

A 16-GHz Triple-Modulus Phase-Switching Prescaler and Its Application to a 15-GHz Frequency Synthesizer in 0.18-μm CMOS

A triple-modulus phase-switching prescaler for high- speed operations is presented in this paper. By reversing the switching orders between the eight 45deg-spaced signals generated by the 8 : 1 frequency divider, the maximum operating frequency of the prescaler is effectively enhanced. With the triple-modulus switching scheme, a wide frequency covering range is achieved. The proposed prescaler is implemented in a 0.18-mum CMOS process, demonstrating a maximum operating frequency of 16 GHz without additional peaking inductors for a compact chip size. Based on the high-speed prescaler, a fully integrated integer-N frequency synthesizer is realized. The synthesizer operates at an output frequency from 13.9 to 15.6 GHz, making it very attractive for wideband applications in Ku-band. At an output frequency of 14.4 GHz, the measured sideband power and phase noise at 1-MHz offset are -60 dBc and -103.8 dBc/Hz, respectively. The fabricated circuit occupies a chip area of 1 mm² and consumes a dc power of 70 mW from a 1.8-V supply voltage