一种用于提取LDD结构n-MOSFET热载流子应力下界面陷阱产生的改进方法

提出了一种新的基于电荷泵技术和直流电流法的改进方法,用于提取LDDn MOSFET沟道区与漏区的界面陷阱产生.这种方法对于初始样品以及热载流子应力退化后的样品都适用.采用这种方法可以准确地确定界面陷阱在沟道区与漏区的产生,从而有利于更深入地研究LDD结构器件的退化机制.     

超深亚微米LDD nMOSFET中的非幸运电子模型效应

通过对采用0.18μm CMOS工艺制造的两组不同沟道长度和栅氧厚度的LDD器件电应力退化实验发现,短沟薄栅氧LDD nMOSFET(Lg=0.18μm,Tox=3.2nm)在沟道热载流子(CHC)应力下的器件寿命比在漏雪崩热载流子(DAHC)应力下的器件寿命要短,这与通常认为的DAHC应力(最大衬底电流应力)下器件退化最严重的理论不一致.因此,这种热载流子应力导致的器件退化机理不能用幸运电子模型(LEM)的框架理论来解释.认为这种"非幸运电子模型效应"是由于最大碰撞电离区附近具有高能量的沟道热电子,在Si-SiO2界面产生界面陷阱(界面态)的区域,由Si-SiO2界面的栅和漏的重叠区移至沟道与LDD区的交界处以及更趋于沟道界面的运动引起的.     

超深亚微米LDD nMOSFET中的非幸运电子模型效应

通过对采用0.18μm CMOS工艺制造的两组不同沟道长度和栅氧厚度的LDD器件电应力退化实验发现，短沟薄栅氧LDD nMOSFET（Lg=0.18μm，Tox=3.2nm）在沟道热载流子(CHC)应力下的器件寿命比在漏雪崩热载流子（DAHC）应力下的器件寿命要短，这与通常认为的DAHC应力（最大衬底电流应力）下器件退化最严重的理论不一致．因此，这种热载流子应力导致的器件退化机理不能用幸运电子模型（LEM）的框架理论来解释．认为这种“非幸运电子模型效应”是由于最大碰撞电离区附近具有高能量的沟道热电子，在Si-SiO2界面产生界面陷阱(界面态)的区域，由Si-SiO2界面的栅和漏的重叠区移至沟道与LDD区的交界处以及更趋于沟道界面的运动引起的．     

0.275μm nMOST's中陷阱辅助隧穿电流对漏端LDD区DCIV谱峰的影响

应用direct-current current voltage(DCIV)和电荷泵(change pumping)技术研究了LDD nMOST's在热电子应力下产生的界面陷阱.测试和分析的结果显示,一股额外的漏端电流影响了DCIV谱峰中表征漏区的D峰.这股电流主要是陷阱辅助隧穿电流.     

应力下LDD nMOSFET栅控产生电流退化特性研究

研究了LDD nMOSFET栅控产生电流在电子和空穴交替应力下的退化特性。电子应力后栅控产生电流减小,相继的空穴注人中和之前的陷落电子而使得产生电流曲线基本恢复到初始状态。进一步发现产生电流峰值在空穴应力对电子应力引发的退化的恢复程度与阈值电压和最大饱和漏电流不同。电子应力中陷落电子位于栅漏交叠区附近的沟道侧I区和LDD侧的II区中氧化层中。GIDL应力中,空穴注入进II区中和了陷落电子,使得产生电流的退化基本得到恢复,但这些空穴并未有效中和I区中的陷落电子,因此阈值电压和最大饱和漏电流退化恢复的程度较小,分别为20%和7%。     

复合栅控二极管新技术提取热载流子诱生的NMOS/SOI器件界面陷阱的横向分布

提出了用复合栅控二极管新技术提取MOS/SOI器件界面陷阱沿沟道横向分布的原理,给出了具体的测试步骤和方法.在此基础上,对具有体接触的NMOS/SOI器件进行了具体的测试和分析,给出了不同的累积应力时间下的界面陷阱沿沟道方向的横向分布.结果表明:随累积应力时间的增加,不仅漏端边界的界面陷阱峰值上升,而且沿沟道方向,界面陷阱从漏端不断向源端增生.     

复合栅控二极管新技术提取热载流子诱生的NMOS/SOI器件界面陷阱的横向分布

提出了用复合栅控二极管新技术提取MOS/SOI器件界面陷阱沿沟道横向分布的原理,给出了具体的测试步骤和方法.在此基础上,对具有体接触的NMOS/SOI器件进行了具体的测试和分析,给出了不同的累积应力时间下的界面陷阱沿沟道方向的横向分布.结果表明:随累积应力时间的增加,不仅漏端边界的界面陷阱峰值上升,而且沿沟道方向,界面陷阱从漏端不断向源端增生.     

漏轻掺杂MOSFET的源漏穿通

测量和分析了1μm LDD MOSFET的穿通特性,与常规结构的MOSFET加以比较.结果表明,LDD结构能够有效地抑制DIBL效应、大幅度地提高短沟道MOSFET的源漏穿通电压.此外,还给出LDD MOSFET源漏穿通机制的定性解释.     

Halo LDD结构多晶硅薄膜晶体管的模拟研究

提出了多晶硅薄膜晶体管的一种Halo LDD新结构,这种结构是在基于LDD结构的基础上,在沟道靠近源、漏端引入高掺杂的Halo区.并利用工艺和器件模拟软件对该Halo LDD P-Si TFT的电学特性进行了分析,并将其与常规结构、LDD结构和Halo结构进行了比较.发现Halo LDD结构的P-si TFT能有效地降低泄漏电流、抑制阈值电压漂移和Kink效应;减少因尺寸减小后所带来的一系列问题.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对p MOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于p MOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是p MOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

Spatial distribution of interface traps in DeMOS transistors

The spatial distribution of interface traps in a p-type drain extended MOS transistor is experimentally determined by the analysis of variable base-level charge pumping spectra. The evolution of the interface trap distribution can be monitored as a function of the hot-carrier stress time. A double peaked interface trap density distribution, located in the spacer oxide, is extracted. The interface trap density in the poly overlapped drift region is constant as a function of stress time. No channel degradation is observed.     

Extraction of the lateral distribution of interface traps in MOSFETs by a novel combined gated-diode technique

A novel combined gated-diode technique for qualitatively extracting the lateral distribution of interface traps in N-MOSFETs is presented in this paper. The key of this technique lies in the recombination–generation current peak originating from the interface trap recombination is being modulated by the drain voltage of the combined forward gated-diode architecture. The extraction principle is introduced in detail and the extraction procedure is also erected. The experimental results qualitatively show that the induced interface traps gradually decrease from the drain and source edges to the channel region while showing the highest value near both edges in N-MOSFETs.     

Characterization of various stress-induced oxide traps in MOSFET'sby using a subthreshold transient current technique

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant     

Profiling interface traps in MOS transistors by the DCcurrent-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 10¹¹ traps/cm² generated by channel hot electron stress     

Origins and characterization of low-frequency noise in GaAsMESFET's grown on InP substrates

An experimental study of the low-frequency noise in GaAs MESFET's grown on InP substrates is reported. The influence of the biases applied to the gate, backgate, and drain in the ohmic region is investigated in order to identify and characterize the 1/f noise origin. We find that this noise can be explained by carrier number fluctuations in the channel and related to trapping phenomena. The traps responsible for this noise are located near the channel-buffer interface. Moreover, the noise behavior exhibits for a well-defined gate voltage, corresponding to the case where the drain current flows near the channel-buffer interface, a GR-type (Lorentzian) noise spectrum emerging from a quite general 1/f noise. This last spectrum corresponds to a single trap level with a density of N_T=10¹⁶ cm^-3 and a time constant τ=1.8 ms which may be attributed to crystal defects present in the GaAs layers     

Analysis of the DCIV peaks in electrically stressed pMOSFETs

This paper presents the effects of Fowler-Nordheim (FN) and hot-carrier (HC) stress in the direct-current current voltage (DCIV) measurements. The effect of interface trapped charge on DCIV curves is reported. Stress-induced oxide charge shifts the DCIV peaks, while stress-induced interface trapped charge causes a spread in the DCIV peaks. It is found that under HC stress, when the absolute value of stress gate voltage changes from low to high, the interface trap spatial location moves from the drain region to the channel region. It is inferred that the generation of oxide charge in the drain region is a two-step process. For short stress times, electrons mainly fill the process-induced neutral oxide traps, while for long stress times, electrons fill the stress created electron traps     

Effects of measurement frequency and temperature anneal on differential gate capacitance spectra observed in hot carrier stressed MOSFET's

Hot carrier generated fixed and interface traps, located at the Si-SiO/sub 2/ interface near the drain junction, are observed from the gate-to-drain capacitance of the MOS transistor, using an AC measurement signal applied to the drain. When the channel is biased in inversion, the drain junction is forward biased and carriers from the AC signal source are readily injected into the channel, leading to charge exchange between the inversion carriers and the traps located in one half of the band gap. In channel depletion, the drain junction is reverse biased, and charge exchange is between the substrate majority carriers and traps located in the other half of the band gap. The charge interaction manifests itself in a differential gate capacitance, extracted from pre- and post-stress gate capacitance voltage curves. The differential capacitance spectrum shows two distinct peaks, which are attributed to the response of donor and acceptor interface traps, located on either half of the band gap. This model is supported by capacitance measurements at different frequencies. Lower frequencies lead to a proportionally larger increase in the depletion regime response. Prolonged stress results in the convolution of the two peaks. A reverse bias on the drain leads to the deconvolution of the spectrum, allowing the two peaks to be clearly resolved. Trap response may be masked by the fixed charge, but this can be overcome by depopulation of trapped electrons or neutralization of trapped holes through elevated temperature anneal. The differential gate-to-drain capacitance allows the electrical identification of both donor and acceptor interface traps in the same device.<>     

A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve