GaAs/Si/AlAs异质结的带阶和GaAs生长温度的影响

用分子束外延 (MBE)设备制备了 Ga As/ Al As和 Ga As/ Si/ Al As异质结 ,通过 XPS分别研究了异质结界面处 Si层厚度为 0 .5 ML 和 1ML 对异质结带阶的调节 ,得到最大调节量为 0 .2 e V;通过 C- V法研究了异质结的Ga As层在不同温度下生长对 0 .5 ML Si夹层的影响 ,得到 Si夹层的空间分布随 Ga As层生长温度的升高而扩散增强的温度效应 ,通过深能级瞬态谱 (DL TS)研究了在上述不同温度下生长的 Ga As层的晶体质量 .     

GaAs/Si/AlAs异质结的DLTS实验研究

利用深能级瞬态谱(DLTS)技术研究了Si夹层和GaAs层不同生长温度对GaAs/AlAs异质结晶体品质的影响.发现Si夹层的引入并没有引起明显深能级缺陷,而不同温度下生长的GaAs/Si/AlAs异质结随着温度的降低,深能级缺陷明显增加,并进行了分析,得到深能级是由Ga空位引起的,在600℃时生长的晶体质量最佳.     

Si/GaAs异质结界面态及其价带不连续性

本文报道用自洽EHT方法研究Si/GaAs异质结界面态分布和价带不连续性。用准共度晶格模型处理晶格失配问题,并对晶格常数作了修正。通过对Si/GaAs(111)、Si/GaAs(111)和Si/GaAs(110)异质结中Si应变和GaAs应变的情况,分别进行计算,得到界面态分布和价带不连续值等物理量,结果表明:它们不仅依赖于组成异质结的两种材料的体性质,而且还依赖于界面晶向和材料应变。文中给出了这些计算结果,并作了初步的讨论。     

AlAs／GaAs,AlAs／Si／GaAs异质结果界结构的电镜研究

原子层掺杂(Atomic Layer Doping)可以在二极管结构中产生一种内部势垒,从而控制半导体的某些电学性能。本工作就是在GaAs衬底上MBE生长AlAs和Si。在测试过程中,我们采用大角度会聚束电子衍射(简称LACBED)和高分辨像(HREM)研究AlAs/GaAs,AlAs/Si/GaAs的界面结构及失配能力。     

GaAs/Si异质结界面性质的理论研究

<正> 随着GaAs集成电路和微波、光电器件的发展,GaAs/Si异质结的研究已引起了广泛的重视。这种异质结综合了Si和GaAs两者的优点,因此,有希望开辟新的应用。国外利用MBE和MOCVD方法长出了比较满意的GaAs/Si异质结,最近南京电子器件研究所黄善祥等利用传统的汽相外延方法也生长出了GaAs/Si异质结。 在已报导的GaAs/Si异质结实验结果中,一致的看法是在界面处形成了SiAs化合物,但界面的真实组成及其性质如何,尚没有足够的实验和理论验证。作者利用普适参数紧束缚方法,从理论上对GaAs/Si异质结界面进行了研究,计算了界面的GaSi和SiAs化合物的键能E_b、自然键长d、力常数K以及弛豫效应等,结果列于下表。     

在Si上集成GaAs LED

美国TI公司中央研究实验室研制成功一种在Si3位CMOS译码器上集成8只GaAs LED阵列.电源电压5V.Si衬底材料为P~-.该实验室采用了如下工艺:(1)先生长CMOS源和漏,然后通过SUi_2/Si_3N_4制作n~+Si,然后再在n~+Si飞上集成GaAs LED;(2)清洗工艺采用H_2SO_4-H_2O_2+2%HF;(3)用常规两步MDE方法生长1.5μmGaAs缓冲层.然后再生长GaAs双异质结LED外延层.     

MBE-GaAs/Si材料应变层的调制光谱研究

本文采用光调制反射光谱(PR),双晶衍射(DCRD),光荧光激发光谱(PL)等技术研究了MBE-GaAs/Si异质结材料GaAs层的应变情况,以及从不同温度快速热退火后GaAs/Si(PR)谱的变化可看出GaAs外延层应变随退火温度增大而增大,GaAs能隙则随之下降,考虑到应力随温度变化因素后这些不同的测试方法所得的结论与(PR)谱结果基本一致。因此用室温光反射调制光谱对于检测室温下GaAs/Si材料的质量,剩余应力等是方便而有力的方法。     

刻槽硅衬底上的GaAs/AlGaAs超晶格材料的微结构特性

用分子束外延在有刻槽的{001}硅衬底上生长了 GaAs/Al_(0.3)Ga_(0.7)As超晶格材料,利用横断面透射电子显微术对非平而异质结的生长行为和微观结构进行了观察.研究结果表明硅衬底上刻槽的几何形状对外延层的微缺陷特性及生长行为有一定影响,和Si{001}晶面相比,Si{113}可能是一个有利于生长半导体异质结的晶面.     

ZnO/Si异质结中的晶界层行为研究

本文利用电容-电压,电流-电压和深能级瞬态谱研究了ZnO/Si异质结的晶界层行为和载流子的输运机制。当存在高密度界面态时,ZnO/Si异质结的载流子输运受到晶界层的控制。我们观察到了有趣的现象,不同测量温度下得到的ZnO/Si异质结正向lnI-V曲线发生交叉,另外得到ZnO/Si异质结的有效势垒高度随着测量温度的下降而下降,这与理想的异质结热发射模型是相矛盾的。本文的随后各节对上面提到的现象做出解释。     

MBE GaAs/Si材料应力性质的研究

用光致发光谱及高分辨率的X射线双晶衍射对 MBE GaAs/Si异质结材料进行研究,发现GaAs外延层和Si衬底存在一定的晶向偏离,整个GaAs外延层呈现双轴张应力,这是GaAs和Si的晶格失配导致的双轴压应力和热膨胀系数失配导致的双轴张应力的总结果.本文根据一定的物理假设,推导出GaAs外延层中的平均应力,表明应力与材料所处的温度相关.据此,本文进一步用光致发光谱测量了25K至 260K温度范围内的应力,发现应力随温度的增大而下降,与理论公式反映的规律吻合.     

Epitaxial growth and characterization of DyP/GaAs, DyAs/GaAs, and GaAs/DyP/GaAs heterostructures

There is a significant interest in the area of improving high temperature stable contacts to III-V semiconductors. Two attractive material systems that offer promise in this area are dysprosium phosphide/gallium arsenide (DyP/GaAs) and dysprosium arsenide/gallium arsenide (DyAs/GaAs). Details of epitaxial growth of DyP/GaAs and DyAs/GaAs by molecular beam epitaxy (MBE), and their characterization by x-ray diffraction, transmission electron microscopy, atomic force microscopy, Auger electron spectroscopy, Hall measurements, and high temperature current-voltage measurements is reported. DyP is lattice matched to GaAs, with a room temperature mismatch of less than 0.01% and is stable in air with no sign of oxidation, even after months of ambient exposure. Both DyP and DyAs have been grown by solid source MBE using custom designed group V thermal cracker cells and group III high temperature effusion cells. High quality DyP and DyAs epilayer were consistently obtained for growth temperatures ranging from 500 to 600°C with growth rates between 0.5 and 0.7 μm/h. DyP epilayers are n-type with electron concentrations of 3 × 10²⁰ to 4 × 10²⁰ cm⁻³, room temperature mobilities of 250 to 300 cm²/V·s, and a barrier height of 0.81 eV to GaAs. DyAs epilayers are also n-type with carrier concentrations of 1 × 10²¹ to 2 × 10²¹ cm⁻³, and mobilities between 25 and 40 cm²/V·s.     

Self-aligned GaAs MISFET's with a low-temperature-grown GaAs gateinsulator

GaAs MISFET's with a low-temperature-grown (LTG) GaAs gate insulator and ion-implanted self-aligned source and drain n⁺ regions are demonstrated. The resistivity and breakdown field of the LTG GaAs insulator were not changed appreciably by implantation and 800°C activation annealing. The gate leakage current remained very low at a value of approximately 1 μA per μm² of gate area at 3 V forward gate bias. Because of the reduced source and drain resistance, the drain saturation current and the transconductance of self-aligned MISFET's increased more than twofold after ion implantation     

GaAs inversion-base bipolar transistor (GaAs IBT)

A completely new type of GaAs bipolar transistor with a base formed by a two-dimensional hole gas has been fabricated. The transistor has no metallurgical base layer but has an extremely thin inversion hole layer working as a base layer. The current gain β = 5.6 at 77 K and β = 17.1 at 300 K was obtained for the common emitter mode.     

GaAs MISHFET的研制

本文介绍一种有别于GaAs MESFET又相似于HEMT结构的器件。采用MBE技术生长i-GaAs/i-GaAlAs/i-GaAs结构,用溅射技术淀积WSi_x,用自对准离子注入形成源-漏区来制备MISHFET。这是一种具有二维电子气的异质结场效应器件。栅电极尺寸为4μm×40μm,测量到的开启电压为+1.4V,跨导为20—25mS/mm,还给出了低温测量结果。     

GaAs的中子嬗变掺杂

文章介绍了ＧａＡｓ的中子嬗变掺杂的优点，砷化镓的ＮＴＤ原理，以及ＮＴＤ－ＧａＡｓ的退火过程，并简要介绍了国外ＧａＡｓ的ＮＴＤ研究进展和结果。     

GaAs MESFET's fabricated on monolithic GaAs/Si substrates

GaAs MESFET's have been fabricated for the first time on monolithic GaAs/Si substrates. The substrates were prepared by growing single-crystal GaAs layers on Si wafers that had been coated with a Ge layer deposited by e-beam evaporation. The MESFET's exhibit good transistor characteristics, with maximum transconductance of 105 mS/mm for a gate length of 2.1 µm.     

高速GaAs ADC与GaAs DAC研制现状

本文叙述了高速GaAs ADC与GaAs DAC的研制现状。着重介绍了在芯片上有T/H电路的闪光型ADC和在芯片上有电流源的DAC,以及它们的性能。     

Application of low temperature GaAs to GaAs/Si

Low Temperature grown GaAs (LT-GaAs) was incorporated as a buffer layer for GaAs on Si (GaAs/Si) and striking advantages of this structure were confirmed. The LT-GaAs layer showed high resistivity of 1.7 × 10⁷ ω-cm even on a highly defective GaAs/Si. GaAs/Si with the LT-GaAs buffer layers had smoother surfaces and showed much higher photoluminescence intensities than those without LT-GaAs. Schottky diodes fabricated on GaAs/Si with LT-GaAs showed a drastically reduced leakage current and an improved ideality factor. These results indicate that the LT-GaAs buffer layer is promising for future integrated circuits which utilize GaAs/Si substrates.     

Ku波段8W GaAs内匹配微波功率FET

Ｋｕ波段８ＷＧａＡｓ内匹配微波功率ＦＥＴ李祖华（南京电子器件研究所，２１００１６）Ｋｕ－Ｂａｎｄ８ＷＧａＡｓＩｎｔｅｒｎａｌｌｙＭａｔｃｈｅｄＭｉｃｒｏｗａｖｅＰｏｗｅｒＧａＡｓＦＥＴ￥ＬｉＺｕｈｕａ（ＮａｎｊｉｎｇＥｌｅｃｔｒｏｎｉｃＤｅｖｉｃｅｓ...     

Structural and photoluminescent characteristics of porous GaAs capped with GaAs

In this paper, we present the results of structural and room temperature photoluminescence studies on porous GaAs (π-GaAs) capped with GaAs. The porous structure formation was confirmed by scanning electron microscopy (SEM) and relatively homogeneous pores of diameters as small as 4 nm was grown along <111>B directions. X-ray diffraction (XRD) investigations confirm the high crystal quality of the capping layer and a lattice mismatch of 4% between the two layers was determined. The room temperature photoluminescence (PL) spectrum of porous GaAs recorded during steady-state excitation shows a strong PL covering the red–blue band. Time resolved photoluminescence (PLRT) investigations provide evidence for the existence of PL components with different origins.