热载流子应力下超薄栅p MOS器件氧化层陷阱电荷的表征

利用电荷泵技术研究了 4nmpMOSFET的热载流子应力下氧化层陷阱电荷的产生行为 .首先 ,对于不同沟道长度下的热载流子退化 ,通过直接的实验证据 ,发现空穴陷阱俘获特性与应力时间呈对数关系 .然后对不同应力电压、不同沟道长度下氧化层陷阱电荷 (包括空穴和电子陷阱俘获 )的产生做了进一步的分析 .发现对于 pMOSFET的热载流子退化 ,氧化层陷阱电荷产生分两步过程 :在较短的应力初期 ,电子陷阱俘获是主要机制 ;而随着应力时间增加 ,空穴陷阱俘获作用逐渐显著 ,最后主导了氧化层陷阱电荷的产生.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对pMOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于pMOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是pMOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对p MOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于p MOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是p MOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

基于DCIV法对pMOSFET热载流子损伤的研究

利用新型的直流电流电压(DCIV)法研究了热载流子应力下的亚微米pMOSFET的氧化层陷阱电荷和表面态产生行为,并对热载流子应力下pMOSFET的阈值电压和线性区漏端电流的退化机制做出了物理解释.实验发现在栅极电压较高的热载流子应力条件下,热载流子引发表面态密度随时间变化的两个阶段:第一阶段,电负性的氧化层陷阱电荷起主导作用,使线性区漏端电流随时间增加;第二阶段,表面态逐渐起主导作用,导致线性电流随时间逐渐减小.     

沟道热载流子导致的 PDSOI NMOSFET's击穿特性

对热载流子导致的 SIMOX衬底上的部分耗尽 SOI NMOSFET's的栅氧化层击穿进行了系统研究 .对三种典型的热载流子应力条件造成的器件退化进行实验 .根据实验结果 ,研究了沟道热载流子对于 SOI NMOSFET's前沟特性的影响 .提出了预见器件寿命的幂函数关系 ,该关系式可以进行外推 .实验结果表明 ,NMOSFET's的退化是由热空穴从漏端注入氧化层 ,且在靠近漏端被俘获造成的 ,尽管电子的俘获可以加速 NMOSFET's的击穿 .一个 Si原子附近的两个 Si— O键同时断裂 ,导致栅氧化层的破坏性击穿 .提出了沟道热载流子导致氧化层击穿的新物理机制     

沟道热载流子导致的PDSOI NMOSFET's击穿特性

对热载流子导致的SIMOX衬底上的部分耗尽SOI NMOSFET's 的栅氧化层击穿进行了系统研究．对三种典型的热载流子应力条件造成的器件退化进行实验．根据实验结果,研究了沟道热载流子对于SOI NMOSFET's前沟特性的影响．提出了预见器件寿命的幂函数关系,该关系式可以进行外推．实验结果表明,NMOSFET's 的退化是由热空穴从漏端注入氧化层,且在靠近漏端被俘获造成的,尽管电子的俘获可以加速NMOSFET's的击穿．一个Si原子附近的两个Si—O键同时断裂,导致栅氧化层的破坏性击穿．提出了沟道热载流子导致氧化层击穿的新物理机制．     

脉冲应力增强的NMOSFET's热载流子效应研究

 本文研究了交流应力下的热载流子效应,主要讨论了脉冲应力条件下的热空穴热电子交替注入对NMOSFET's的退化产生的影响.在脉冲应力下,阈值电压和跨导的退化增强.NMOSFET's在热空穴注入后,热电子随后注入时,会有大的退化量,这可以用中性电子陷阱模型和脉冲应力条件下热载流子注入引起的栅氧化层退化来解释.本文还定量分析研究了NMOSFET's退化与脉冲延迟时间和脉冲频率的关系,并且给出了详细的解释.在脉冲应力条件下,器件的热载流子退化是由低栅压下注入的热空穴和高栅压下热电子共同作用的结果.     

超薄栅MOS器件热载流子应力下SILC的产生机制

通过测量界面陷阱的产生,研究了超薄栅nMOS和pMOS器件在热载流子应力下的应力感应漏电流(SILC).在实验结果的基础上,发现对于不同器件类型(n沟和p沟)、不同沟道长度(1、0.5、0.275和0.135μm)、不同栅氧化层厚度(4和2.5nm),热载流子应力后的SILC产生和界面陷阱产生之间均存在线性关系.这些实验证据表明MOS器件减薄后,SILC的产生与界面陷阱关系非常密切.     

脉冲应力增强的NMOSFET′s热载流子效应研究

本文研究了交流应力下的热载流子效应 ,主要讨论了脉冲应力条件下的热空穴热电子交替注入对NMOSFET′s的退化产生的影响 .在脉冲应力下 ,阈值电压和跨导的退化增强 .NMOSFET′s在热空穴注入后 ,热电子随后注入时 ,会有大的退化量 ,这可以用中性电子陷阱模型和脉冲应力条件下热载流子注入引起的栅氧化层退化来解释 .本文还定量分析研究了NMOSFET′s退化与脉冲延迟时间和脉冲频率的关系 ,并且给出了详细的解释 .在脉冲应力条件下 ,器件的热载流子退化是由低栅压下注入的热空穴和高栅压下热电子共同作用的结果     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

A comparison of hot-carrier degradation in tungsten polycide gateand poly gate p-MOSFETs

A study is made of hot-carrier immunity of tungsten polycide and of non-polycide, n⁺ poly gate, buried-channel p-MOSFETs, under conditions of maximum gate current injection. Increased hot-carrier degradation is observed for WSi_x p-MOSFETs under low drain voltage stress, where trap filling by injected electrons is the dominant degradation process. Stress-induced damage evaluated by gate-to-drain capacitance C_gd^s measurement shows increased susceptibility to electron trapping in the WSi_x device. F-induced oxide bulk defects introduced during polycidation may be responsible for the increased trapping observed. In addition, a significant decrease in electron detrapping rate is observed, which suggests a deeper energy distribution of F-related traps. The greater susceptibility to electron trapping, coupled with a decrease in electron detrapping rate, result in the reduction in DC hot-carrier lifetime over four orders of magnitude (based on ΔV_t=50 mV criterion) under normal operating voltages. As hot-carrier effects in p-MOSFETs continue to be a concern for effective channel lengths less than 0.5 μm, the reduced hot-carrier lifetime of WSi_x p-MOSFETs suggests that WF₆-based silicidation may not be appropriate for deep submicrometer CMOS devices     

Device scaling effects on hot-carrier induced interface andoxide-trapped charge distributions in MOSFETs

The influence of channel length and oxide thickness on the hot-carrier induced interface (N_it) and oxide (N_ot) trap profiles is studied in n-channel LDD MOSFET's using a novel charge pumping (CP) technique. The technique directly provides separate N_it and N_ot profiles without using simulation, iteration or neutralization, and has better immunity from measurement noise by avoiding numerical differentiation of data. The N_it and N_ot profiles obtained under a variety of stress conditions show well-defined trends with the variation in device dimensions. The N_it generation has been found to be the dominant damage mode for devices having thinner oxides and shorter channel lengths. Both the peak and spread of the N_it profiles have been found to affect the transconductance degradation, observed over different channel lengths and oxide thicknesses. Results are presented which provide useful insight into the effect of device scaling on the hot-carrier degradation process     

Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

Impact of snapback-induced hole injection on gate oxide reliabilityof N-MOSFETs

N-channel MOSFETs associated with CMOS output driver circuits are often driven deep into snapback during electrostatic discharge (ESD) events. The charge-pumping technique is used to show significant hole trapping in the oxide resulting from snapback bias conditions. Floating-gate measurements verify that significant hole current flows through the oxide during snapback. It is noted that snapback-induced hole injection can dramatically reduce gate oxide charge to breakdown and explains reduced hot-carrier lifetimes after snapback stress. Snapback stress results in oxide damage that is in many ways similar to that found during hot-carrier stress and radiation damage. These long-term reliability concerns limit the maximum allowable snapback current     

Simulation of substrate hot-electron injection

Electron trapping in thin oxide and interface state generation has been investigated using a constant-current stressing technique. Assuming finite-temperature Fowler-Nordheim tunneling, semiempirical simulations of voltage versus stress time behavior were obtained for an MOS diode. A trapped charge model was used to simulate voltage versus stress-time behavior. The comparison between measurement and simulation results yields information about trapped charges in the oxide and at the oxide-substrate interface. The model can serve as the basis for improved understanding of the more complex phenomenon of channel hot-carrier injection in MOS transistors     

Investigation of interface traps in LDD pMOST's by the DCIV method

Interface traps in submicron buried-channel LDD pMOSTs, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOSTs. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. However, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high