A CMOS digitally programmable filter technique for VLSI applications

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current amplifiers (DCCAs) to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed analog/digital systems, the digital tuning feature of the proposed approach allows direct interfacing with the digital signal processing (DSP) part. Basic building blocks such as digitally programmable amplifiers, integrators, and simulated active inductors are given. Systematic designs of second-order filters are presented. Fully differential architectures of the proposed circuits are developed. Experimental results obtained from 0.5 μm standard CMOS chips are provided.     

VLSI CMOS模拟集成电路可靠性仿真设计技术

随着超大规模CMOS模拟集成电路工艺技术进入纳米阶段,模拟集成电路面临着日益严峻的可靠性挑战,可靠性仿真设计技术已经成为提升电路固有可靠性的重要途径.对现有的模拟集成电路可靠性仿真设计的文献资料进行了总结,探讨了集成电路可靠性仿真分析的高效方法,这些方法能够帮助电路设计师对电路进行分析,并找出其中的薄弱环节.介绍了典型的更具适应性和自愈能力的模拟集成电路设计技术.     

Analog components for the VLSI of neural networks

Principles of operation and basic building blocks of artificial neural networks are described. Deterministic components, comprising variable linear conductance devices and components used for processing elements, are discussed. These devices are analyzed using SPICE. The reasons for using simple analog circuits rather than digital circuits are examined     

A programmable analog CMOS synapse for neural networks

This paper presents a programmable analog synapse for use in both feedforward and feedback neural networks. The synapse consists of two complementary floating-gate MOSFETs which are programmable in both directions by Fowler-Nordheim tunneling. The P-transistor and the N-transistor are programmable independently with pulses of different amplitude and duration, and hence finer weight adjustment is made possible. An experimental 4×4 synapse array has been designed, which in addition has 32 analog CMOS switches and x–y decoders to select a synapse cell for programming. It has been fabricated using a standard 2-m, double-polysilicon CMOS technology. Simulation results confirm that output current of synapse is proportional to the product of the input voltage and weight and also shows both inhibitory and excitatory current. Current summing effect has been observed at the input of a neuron. This array is designed using modular and regular structured elements, and hence is easily expandable to larger networks.     

基于CMOS对数域积分器的小波变换模拟VLSI实现

提出了一种基于CMOS对数域积分器的连续Marr小波变换模拟VLSI实现方法.构造了Marr母小波时域逼近函数模型,用Levenbery-Marquardt非线性最小二乘法求解模型参数最优解,得到母小波逼近函数.设计了以CMOS对数域积分器为积木块的小波变换电路,该电路由冲激响应为母小波逼近函数及其伸缩函数的滤波器组构成,滤波器组采用低灵敏度的IFLF结构进行综合.SPICE仿真结果表明该方法的可行性.     

Novel CMOS sampled-data VLSI implementation of artificial neural networks

A mixed-mode VLSI implementation of artificial neural networks offers a tradeoff solution for speed, area saving, and flexibility. A novel CMOS sampled-data programmable synapse and a simple CMOS analogue neuron have been developed. Using a 1.2 mu m CMOS technology, the synapse consumed 120*120 mu m/sup 2/ and the neuron consumed 120*260 mu m/sup 2/.<>     

A programmable analog cellular neural network CMOS chip for highspeed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4×4 CNN prototype system has been designed in a 2.4 μm CMOS technology and successfully tested. The cell density is 380 cells/cm² and the cell time constant is 10 μs. The current drain for a typical template is 40 μA/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128×128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies     

CMOS VLSI设计技术

本文从电路组态,逻辑组态、匹配技术和设计方法上讨论了CMOS VLSI设计技术,以及如何实现高速低功耗和高门密度设计.     

Motion Perception Using Analog VLSI

Motion perception is arguably a fundamental mechanism used by natural species to accomplish a number of tasks, such as navigating freely in an unknown environment. Traditional motion perception methods tend to be computationally intensive, requiring powerful computers and large memories. However, by copying biological mechanisms, such as elementary motion discrimination at the early stages of the visual processing paths, it should be possible to build small and efficient motion perception systems. This paper describes the manner in which a simple motion perception model based on the insect visual system has been implemented using mixed analog/digital VLSI. The device has been fabricated in a 2 micron double metal, double polysilicon process, and comprises 61 photo-detectors, and associated analog and digital circuitry. While not entirely successful in that component mismatches hamper the detection of dark-to-bright changes in contrast, the results clearly show the feasibility of using such a device in autonomous control systems.     

Analog VLSI neural networks: implementation issues and examples inoptimization and supervised learning

Time-critical neural network applications that require fully parallel hardware implementations for maximal throughput are considered. The rich array of technologies that are being pursued is surveyed, and the analog CMOS VLSI medium approach is focused on. This medium is messy in that limited dynamic range, offset voltages, and noise sources all reduce precision. The authors examine how neural networks can be directly implemented in analog VLSI, giving examples of approaches that have been pursued to date. Two important application areas are highlighted: optimization, because neural hardware may offer a speed advantage of orders of magnitude over other methods; and supervised learning, because of the widespread use and generality of gradient-descent learning algorithms as applied to feedforward networks     

The formation of shallow low-resistance source—Drain regions for VLSI CMOS technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-µm transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p⁺regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n⁺and p⁺junction depths are 0.22 µm and of 8 Ω/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.     

Analog circuits in ultra-deep-submicron CMOS

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.     

Low Voltage Rail to Rail CMOS Current Feedback Operational Amplifier and its Applications for Analog VLSI

This paper presents a new CMOS current feedback operational amplifier (CFOA) with rail to rail swing capability at all terminals. The circuit operates as a class AB for lower power consumption. Besides operating at low supply voltages of ±1.5 V, the proposed CFOA has a standby current of 200 A. The proposed CFOA circuit is thus a versatile building block for low voltage low power applications. The applications of the CFOA to realize a transconductor/multiplier cell, MOS-C differential integrator, MOS-C bandpass filter and MOS-C oscillator are given. PSpice simulations based on 1.2 m level three parameters obtained from MOSIS are given.     

Quadruple-well CMOS for VLSI technology

A novel process has been developed to fabricate high-density CMOS with four wells. These wells are self aligned to increase packing density. Two of them are relatively deep wells used to optimize both n- and p-channel active devices. The other two are shallow wells under field oxide to form channel stops for both device types. The channel stops provide rigorous isolation among similar devices and between the devices of the opposite polarity. Subthreshold leakage currents in isolation regions are <0.05 pA/µm when devices are biased at <16.5 V. The channel stops also suppress lateral parasitic bipolar action. To reduce the vertical bipolar gain, a new process technique employing a double-retrograde well and transient annealing has been established. For the CMOS structure with 2-µm p⁺-to-p-well spacing, we have eliminated latchup by suppressing the beta product to below unity. Moreover, the quadruple-well approach has produced active n- and p-channel FET's with excellent characteristics such as low threshold voltage (∼±0.5 V), low subthreshold slope (≲95 mV/dec), low contact resistivity (∼10^-7Ω-cm²), and high channel mobility (620 and 210 cm²/V . s).     

Selective epitaxy for CMOS VLSI

Scaling CMOS for VLSI is difficult owing to increasing latchup susceptibility and lateral diffusion of the well which limits packing density. A novel solution to these problems is presented, using selective epitaxial deposition to refill etched wells. In conjunction with a buried-layer implant, a retrograde well profile is achieved with a low sheet resistivity (440 Ω), giving reduced latchup susceptibility. Shallow wells can be used (typically 1 µm) with source/drain-to-well breakdown voltages greater than 9.5 V. Transistor characteristics are good with a long-channel mobility of 192 cm²/V.s and subthreshold slope of 100-mV/decade for a 2.5-µm channel length.     

Parasitic transistor effects in CMOS VLSI

Parasitic field-effect transistor (FETs) and bipolar junction transistors (BJTs) in a CMOS circuit are described, along with their interactions with each other and their effect on circuit performance. The results are considered to be useful for setting up design rules between n-channel and p-channel active transistors in CMOS IC layout. Novel parasitic transistors associated with next-generation VLSI technologies, such as trench isolation and silicon-on-insulator, are discussed briefly     

Iddq testing for CMOS VLSI

It is little more than 15-years since the idea of Iddq testing was first proposed. Many semiconductor companies now consider Iddq testing as an integral part of the overall testing for all IC's. This paper describes the present status of Iddq testing along with the essential items and necessary data related to Iddq testing. As part of the introduction, a historical background and discussion is given on why this test method has drawn attention. A section on physical defects with in-depth discussion and examples is used to illustrate why a test method outside the voltage environment is required. Data with additional information from case studies is used to explain the effectiveness of Iddq testing. In Section IV, design issues, design styles, Iddq test vector generation and simulation methods are discussed. The concern of whether Iddq testing will remain useful in deep submicron technologies is addressed (Section V). The use of Iddq testing for reliability screening is described (Section VI). The current measurement methods for Iddq testing are given (Section VII) followed by comments on the economics of Iddq testing (Section VIII). In Section IX pointers to some recent research are given and finally, concluding remarks are given in Section X     

A Smart-Scanning Analog VLSI Visual-Attention System

We have implemented a hardware model of selective visual attention within the neuromorphic, analog VLSI paradigm. The system includes a highly-parallel winner-take-all selection with excitatory and inhibitory influences. The selection specifies positions of attention based on an array of intensity levels, which comprise a primitive saliency map. The excitation and inhibition control the strategy for shifts of attention from one position to the next. The combination of these fundamental building blocks demonstrates emergent properties that can be observed in real time due to the parallel hardware implementation. The system behaves as a smart-scanning sensor array. The basic characteristics of the scanning pattern are controlled by setting a number of analog parameters. In this paper we describe the system, focusing on the role that inhibition plays in the redirection of attention. We show experimental results from one-dimensional implementations of the hardware model. Analysis that explains the expected behavior for the two-element mode of operation is presented. The theoretical predictions are compared to experimental results.     

A Low-Power Wide-Dynamic-Range Analog VLSI Cochlea

Low-power wide-dynamic-range systems are extremely hard to build. The biological cochlea is one of the most awesome examples of such a system: It can sense sounds over 12 orders of magnitude in intensity, with an estimated power dissipation of only a few tens of microwatts. In this paper, we describe an analog electronic cochlea that processes sounds over 6 orders of magnitude in intensity, and that dissipates 0.5 mW. This 117-stage, 100 Hz to 10 KHz cochlea has the widest dynamic range of any artificial cochlea built to date. The wide dynamic range is attained through the use of a wide-linear-range transconductance amplifier, of a low-noise filter topology, of dynamic gain control (AGC) at each cochlear stage, and of an architecture that we refer to as overlapping cochlear cascades. The operation of the cochlea is made robust through the use of automatic offset-compensation circuitry. A BiCMOS circuit approach helps us to attain nearly scale-invariant behavior and good matching at all frequencies. The synthesis and analysis of our artificial cochlea yields insight into why the human cochlea uses an active traveling-wave mechanism to sense sounds, instead of using bandpass filters. The low power, wide dynamic range, and biological realism make our cochlea well suited as a front end for cochlear implants.     

Analog VLSI Stochastic Perturbative Learning Architectures

We present analog VLSI neuromorphic architectures fora general class of learning tasks, which include supervised learning,reinforcement learning, and temporal difference learning. Thepresented architectures are parallel, cellular, sparse in globalinterconnects, distributed in representation, and robust to noiseand mismatches in the implementation. They use a parallel stochasticperturbation technique to estimate the effect of weight changeson network outputs, rather than calculating derivatives basedon a model of the network. This model-free technique avoidserrors due to mismatches in the physical implementation of thenetwork, and more generally allows to train networks of whichthe exact characteristics and structure are not known. With additionalmechanisms of reinforcement learning, networks of fairly generalstructure are trained effectively from an arbitrarily suppliedreward signal. No prior assumptions are required on the structureof the network nor on the specifics of the desired network response.