Architecture and design of NX-2700: a programmable single-chip HDTVall-format-decode-and-display processor

This paper describes the architecture, functionality, and design of NX-2700, a digital television and media processor chip from Philips Semiconductors. The NX-2700 is the second generation of an architectural family of programmable multimedia processors targeted at the digital television (DTV) markets, including the United States Advanced Television Systems Committee (ATSC) DTV-standard-based applications. The chip not only supports all of the 18 ATSC formats from standard-definition to wide-angle, high-definition video, but has also the power to handle high-definition television (HDTV) video and audio source decoding (high-level MPEG-5 AC-3 and ProLogic audio, closed captioning, etc.) as well as the flexibility to process advanced interactive services. NX-2700 is a programmable processor with a very powerful, general-purpose very long instruction word (VLIW) central processing unit (CPU) core that implements many nontrivial multimedia algorithms, coordinates all on-chip activities, and runs a small real-time operating system. The CPU core, aided by an array of peripheral devices (multimedia coprocessors and input-output units) and high-performance buses, facilitates concurrent processing of audio, video, graphics, and communication-data     

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters

This paper presents a single-chip programmable platform that integrates most of hardware blocks required in the design of embedded system chips. The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable first-in-first-out (FIFO) memories, control circuitry, and on-chip memories. For rapid thread switch, a multithreaded processor equipped with a hardware thread scheduling unit is adopted, and configurable logics are grouped into clusters for IP-based design. By integrating both the multithreaded processor and the configurable logic on a single chip, high-level language-based designs can be easily accommodated by performing the complex and concurrent functions of a target chip on the multithreaded processor and implementing the external interface functions into the configurable logic clusters. A 64-mm/sup 2/ prototype chip integrating a four-threaded MT-RISC, three CLCs, programmable FIFOs, and 8-kB on-chip memories is fabricated in a 0.35-/spl mu/m CMOS technology with four metal layers, which operates at 100-MHz clock frequency and consumes 370 mW at 3.3-V power supply.     

带有可编程视频接口单元的单芯片MPEGⅡ视音频编解码器SM2288

1.概述 美国视讯科技有限公司(Stream Machine)公司所推出的低成本,高性能,单芯片的MPEG-2音频视频编解码产品,是由一个RISC(精简指令集运算)芯核,一个24位DSP(数字信号处理器),视频音频接口单元及多个专用处理单元组成。该产品的可编程视频接口单元对多模式的前,后处理及OSD(屏幕显示)有着强大的支持功能。其CODEC(多媒体数字信号编解码器)更是采用了0.18微米CMOS工艺技术的标准信元库。     

Micro/370: a 32-bit single-chip microprocessor

A 32-bit single-chip microprocessor is described that directly implements 102 System/370 instructions and supports the emulation of the rest of the instructions. It is fabricated using a 2-/spl mu/m polysilicon-gate NMOS technology with two levels of aluminium. The chip is 10/spl times/10 mm/SUP 2/ with 200000 transistor sites. It is designed for a 10-MHz clock at worst case and has been operated at 18 MHz with a 3-W power dissipation. The design and verification methodologies and the testing consideration are also described.     

Simulation of a programmable signal processor

Although simulation, in general, is a very widely used technique, simulation of a complex processor as a tool for v microprogram development is only of recent origin. A signal processor has, quite often, special features like multiple storage and computational modules functioning in parallel, real-time devices, etc. The problems connected with simulating these features are discussed here in the context of a specific architecture. An interactive debugger, incorporated as a special feature of the simulator is also presented, which is an invaluable aid in microprogram debugging.     

一种可编程宽带放大器的设计

以AT89S51单片机和FPGA为控制核心,利用可编程增益放大器THS7001和可变增益放大器AD603,设计一种可编程精密宽带放大器.测试结果表明:该可编程宽带放大器的增益范围为-6～70 dB.通频带为40 Hz-15 MHz.低噪声,并具有自动增益控制功能,动态范围达60 dB.     

Design and application of a programmable pulse distributor

The unit distance property of the Gray code can be used in pulse distributor circuits which are hazard-free. A modified synchronous Gray-code counter is used as the basis of a programmable pulse distributor described in this letter. The complete circuit is iterative in its interconnection pattern and therefore can be extended easily. A possible application of this type of pulse distributors, as a rate multiplier is also considered.     

I.McIC: a single-chip MPEG-2 video encoder for storage

I.McIC is a single-chip MPEG-2 video encoder for consumer storage applications. It supports both intra- and inter-coding mode to achieve bit rates from 5-15 Mb/s. It contains a recursive motion estimator, a programmable buffer/bit-rate controller, and a temporal noise-reduction stage. The resulting IC has 4.5×10⁶ transistors and measures 192 mm² in a 0.5-μm process. I.McIC was designed using mainly high-level synthesis tools. High-throughput fixed MPEG functions are performed by dedicated hardware. The remainder is performed in software by an embedded application-specific instruction-set processor with downloadable microcode to suit the IC for different applications of video coding     

Terahipas: a modular and expandable terabit/second hierarchicallymultiplexing photonic ATM switch architecture

A terabit/second hierarchically multiplexing photonic asynchronous transfer mode (ATM) switch network architecture, called Terahipas, is proposed. It combines the advantages of photonics (a large bandwidth for transport of cells) and electronics (advanced logical functions for controlling, processing, and routing). It uses a hierarchical photonic multiplexing structure in which several tens of channels with a relatively low bit rate, say 2.4 Gb/s, are first time-multiplexed on an optical highway by shrinking the interval between optical pulses, then a number of optical highways are wavelength-multiplexed (or space-division multiplexed). As a result, the switch capacity can be expanded from the order of 100 Gb/s to the order of 10 Tb/s in a modular fashion. A new implementation scheme for cell buffering is used for eliminating the bottleneck when receiving and storing concurrent optical cells at bit rates as high as 100 Gb/s. This new architecture can serve as the basis of a modular, expandable, high-performance ATM switching system for future broad band integrated service digital networks (B-ISDN's)     

低功耗可编程定时器集成电路的设计

介绍了一种低功耗、高精度、高稳定性可编程定时器专用集成电路的设计,对其中的稳定性电路、低功耗问题进行了研究和分析。该电路的静态工作电流为7．8微安。     

FDTD method coupled with FFT: a generalization to open cylindricaldevices

The extension of a numerical method, based on an FDTD algorithm coupled with FFT, is presented. It can be widely applied to the analysis of axially symmetric passive microwave devices. By incorporating the proper radiation conditions in the algorithm, its capacity to deal with the study of open systems is shown; this allows the determination of its quality factor, as well as the resonant frequency and the spatial distribution of the modes. On the other hand, the proper performance of the technique has been verified (stability of the algorithm, accuracy of results) for modes of high angular dependence     

Analog circuits for a single-chip infrared controlled hearing aid

All analog circuits for a remotely controllable subminiature hearing aid are presented. It is feasible to integrate all circuits together with an I²L decoder on a single bipolar chip. The volume level and the cutoff frequency of a high-pass filter can be controlled. Besides, the device can be remotely switched at microphone and telephone coil, and switched into a standby mode. All circuits presented have been tested with a semicustom realization.     

非基2点FFT处理器的设计及实现

在总结已有的FFT实现方法基础上,提出了一种通用FFT处理器的设计;这种FFT实现结构可支持非基2点FFT,硬件资源得到了优化,处理速度可以满足高清晰度数字电视地面传输系统的要求.     

A digitally programmable delay element: design and analysis

Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in integrated circuits (ICs). Delay elements are also used in delay locked loops (DLLs). Although, a few types of digitally controlled delay elements have been proposed, an analytical expression for the delay of these circuits has not been reported. In this paper, we propose a new delay element architecture and develop an analytical equation for the output voltage and an empirical relation for the delay of the circuit. The proposed circuit exhibits improved delay characteristics over previously reported digitally controlled delay elements.     

A single-chip Zero-IF down-converter in SiGe:C BiCMOS technology for WLAN 802.11a

This paper presents the contamination levels, obtained applying the Equivalent Salt Deposit Density ESDD methodology in nine distribution circuits and five substations, belonging to ELECTRICARIBE S.A. E.S.P., and located in the north area of Barranquilla, the main Colombian Atlantic Ocean port. The paper shows the different study stages such as the sampling places selection and configuration, the ESDD measurement procedures and the results evaluation applying statistical techniques.     

Design of a programmable length FIFO memory and its controller

This paper describes the CMOS design of a first-in, first-out (FIFO) memory. The design is based on 2μ. meter CMOS technology and can operate with a 20 MHz clock. The length of the FIFO is programmable, resulting in minimum data ripple through time, for applications not requiring the full length.     

High-speed architecture for a programmable frequency divider and adual-modulus prescaler

We present a prescaler architecture that is suitable for high-speed CMOS applications. We apply the architecture to a 4/5 and an 8/9 dual-modulus prescaler and obtain a measured maximum clock frequency of 1.90 GHz in a standard 0.8 μm CMOS bulk process. This is 13% faster than the traditional prescaler architecture keeping the same power consumption. We also apply the key part of the prescaler to a divide-by-N circuit reaching 1.75 GHz. This is three times faster than any previously reported CMOS implementation and comparable to GaAs implementations     

Systolic FFT Processors: A Personal Perspective

This paper provides a personal perspective on developments in the implementation of two systolic fast Fourier transform processors over the last 25 years and identifies some of the lessons learned. This has been a period of tremendous advancements in integrated circuit technology that is demonstrated by the resulting processors. The first processor is the Modular Transform Processor that was developed at TRW in the 1982–1984 time frame using VLSI technology. It is a set of six large circuit boards that computes 4,096-point fast Fourier transforms using 22-bit floating-point arithmetic at sustained data rates of 40 MSPS. The second processor is a single ASIC chip systolic FFT processor developed by the Mayo Foundation in the 2001–2002 time frame that computes 4,096-point FFTs using 16-bit fixed-point arithmetic at sustained data rates of 200 MSPS. Some thoughts on the future directions of systolic FFT processor development are offered. Future systems will compute large transforms (e.g., 16 K-point to 1 M-point) at high data rates (e.g., 500 MSPS to 1 GSPS), will employ more precise arithmetic (e.g., 32-bit single precision IEEE Standard floating-point arithmetic), will consume very low power (e.g., on the order of one watt) and will be realized on a single chip.     

流水线结构FFT/IFFT处理器的设计与实现

针对实时高速信号处理的要求，设计并实现了一种高效的FFT处理器。在分析了FFT算法的复杂度和硬件实现结构的基础上，处理器采用了按频率抽取的基—4算法，分级流水线以及定点运算结构。可以根据要求设置成4P点的FFT或IFFT。处理器可以对多个输入序列进行连续的FFT运算，消除了数据的输入输出对延时的影响。平均每完成一次N点FFT运算仅需要Ⅳ个时钟周期。整个设计基于Verilog HDL语言进行模块化设计。并在Altera公司的Cyclone Ⅱ器件上实现。