高帧频DVI接口彩色CMOS数字相机系统设计

针对高帧频彩色CMOS图像传感器在机器视觉高速成像领域中的应用,本文介绍利用高性能可编程逻辑器件FPGA实现CMOS图像传感器MI-MV13的高速驱动时序的设计,并且在FPGA内部设计了高速FIFO缓存器和双口RAM来完成Bayer彩色阵列图像数据的实时同步转换输出RGB彩色分量。最终由2片专用DVI接口集成芯片SiI178实现了DVI-IDualLink模式的高帧频高分辨率彩色图像输出,DVI接口方便显示终端和高速存储设备链接。该相机系统具有集成度高、低功耗、接口通用紧凑、传输带宽高的优点。     

A multipurpose circuit to read out and digitize pixel signal for low-power CMOS imagers

A complementary metal oxide semiconductor (CMOS) image sensor with a resolution of 128 × 128 pixels is presented in this paper in which pixel signal readout, noise suppression, and comparing operations are performed by one circuit during two steps: reading and conversion. The main idea of this work is to combine three main operations of an image sensor in one circuit. This method helps to decrease power consumption, silicon area, total noise, and imaging time. The total power consumption of the imager is 11 mW with a 2.5-V power supply and 40-fps frame rate. The pixel layout size is 10 × 10 μm² with a fill-factor of 81%. The analog to digital converter (ADC) resolution is 10 bits, and the error resulted from the proposed circuit is about ±0.5 least significant bit (LSB). The proposed CMOS image sensor was designed based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm CMOS technology and was simulated by CADENCE SPECTRE circuit simulator. This circuit can be proposed for a CMOS imager with highly accurate and efficient power consumption.     

CMOS图像传感器接口

文中介绍基于ARM core的SOC芯片中CMOS图像传感器接口IP模块的设计方案.该IP模块连接在AHB总线和外部的CMOS图像传感器之间,完成对高速图像数据的采集和传输,并能够为后续的图像处理提供统计数据.经过验证,该模块可以完成每帧200万像素的图像数据传输.     

Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger‐wave propagations, extensively used in various image‐processing algorithms. The circuit operates in a continuous‐time mode, achieving high operational performance and low‐power consumption. An integrated circuit with proof‐of‐concept array of 24×60 cells has been fabricated in a 0.35µm three‐metal CMOS process and tested. Occupying only 16×8µm² the binary wave‐propagation cell is designed to be used as a co‐processor in general‐purpose processor‐per‐pixel arrays intended for focal‐plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.     

非致冷型红外焦平面阵列读出电路的研究

论文为非制冷型红外焦平面阵列设计了一种读出电路,该红外传感器阵列采用非制冷型硅二极管作为信号采集元件。该电路的设计与仿真采用了UMC18的工艺库。论文详细描述了小信号放大部分、时序选择部分的电路实现。     

基于FPGA的CMOS成像电路设计

为满足科研和工业领域中对于高分辨率工业相机的需求,针对大靶面CMOS探测器CMV20000设计了成像电路。介绍了CMV20000探测器芯片的主要功能特点,利用FPGA实现了探测器控制信号的驱动和高速LVDS串行图像数据的接收。采用动态相位调整技术校正16路LVDS高速串行数据的相位差、实现了图像数据的同步接收、高速串并转换,对接收到的图像进行了重构并将其通过CameraLink接口进行输出。利用测试图像对成像系统进行了功能验证,并对实际景物进行了成像试验,试验结果表明,系统输出帧频最高达30fps,图像信噪比约为35dB,系统成像质量满足指标需求。     

A new two‐step single slope A/D converter for using in CMOS image sensors

This paper presents a high‐speed, high‐resolution column parallel analog‐to‐digital converter (ADC) with global digital error correction. Proposed A/D converter is suitable for using in high‐frame‐rate complementary metal–oxide–semiconductor (CMOS) image sensors. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11‐bit ADC is designed in 0.25‐µm CMOS technology. Moreover, an overall signal‐to‐noise ratio of 63.8 dB can be achieved at 0.5Msample/s. The power dissipation of all 320 column‐parallel ADCs with the peripheral circuits consume 76 mW at 2.5‐V supplies. Copyright © 2012 John Wiley & Sons, Ltd.     

高速CMOS相机图像采集系统关键技术研究

为满足某靶场弹丸炸点测试中拍摄帧频高、实时记录性强等要求,本文介绍了一种高帧频CMOS图像采集系统。选用帧频250帧每秒的LUPA-300作为高帧频图像传感器,通过FPGA实现对图像传感器的参数配置与图像数据处理,并运用PCI图像采集卡实现图像数据的存储与显示。实验结果表明该系统结构简单、成像清晰稳定,拍摄速度快,可应用于高速目标的拍摄。     

航天遥感TDICCD相机星上振动实时检测

为了对航天遥感相机焦平面振动进行实时检测,提出了一种利用CMOS图像传感器和快速灰度投影算法的振动实时检测方案。首先,分析了航天遥感相机焦面振动检测系统要满足的条件,提出了一种在焦面空闲处安装CMOS图像传感器的结构来获取图像序列,然后对传统灰度投影算法进行了改进并利用该算法计算了图像序列间的振动量,最后,利用FPGA对算法进行了实现。理论分析和实验结果均表明,提出的方案能满足航天遥感相机对焦面振动检测的要求。     

Realization and characterization of 8×8 resonant cavity LEDarrays mounted onto CMOS drivers for POF-based interchipinterconnections

An 8×8 array of resonant-cavity light emitting diodes (RCLED's) emitting at 980 nm and flip-chip mounted onto complimentary metal-oxide-semiconductor (CMOS) integrated drivers, is presented. The RCLED's are optimized for maximal extraction efficiency into the numerical aperture of polymer optical fibers (NA=0.5) and minimal optical crosstalk. Design of the optimal cavity structure is presented, and 8×8 arrays are realized and mounted directly onto standard CMOS chips using a solder reflow technique. The CMOS integrated drivers are designed for high-speed operation and low-power consumption, and are realized in 0.8 and 0.6-μm CMOS technology. The electrooptical modules have been realized and characterized, and over 50-μW optical power coupled to POF at 3-mA drive current is reported. Open eye diagrams at operation speed up to 250 Mb/s are presented. These characteristics are compatible with CMOS integrated low-power receivers     

CMOS Baseline Tracking and Cancellation Instrumentation for Nanoparticle-Coated Chemiresistors

Chemiresistor (CR) sensors and sensor arrays coated with thiolate-monolayer-protected gold nanoparticle (MPN) interfaces show great promise as detectors in gas-chromatographic microsystems with applications in biomedical and environmental analysis including breath biomarkers of disease. This paper describes a new readout circuit that overcomes the wide range of baseline resistances and drift in baseline values inherent to MPN-coated CRs to achieve a 57 ppm readout resolution. The 0.5-mum CMOS circuit operates at 5 V and provides a response resolution of 74 muV. It can cancel baseline voltages from 0.3 to 4.3 V with an accuracy of 4.2 mV and can track and compensate for drifts up to 30 mV/min. Performance was verified with MPN-coated CRs, where drift was measured and effectively cancelled. The circuit topology and size support an on-chip MPN-coated CR sensor array.     

一种多CMOS图像传感器同步曝光方法的研究与实现

为了提高多CMOS图像传感器同步曝光精度,本文给出了一种参数配置同步曝光设计方法。采用Micron公司1／2英寸300万像素CMOS数字图像传感器,通过其串行通信读写协议对传感器进行实时编程,获得了比实际系统设计要求快约29倍的微秒级同步曝光精度。给出了FPGA软件仿真结果和基于硬件平台的SignalTapⅡ测试结果。给出了参数同步配置方法在实际应用中的测试结果。     

Topographic cellular active contour techniques: theory,implementations and comparisons

This paper overviews some massively parallel topographic cellular computational approaches proposed for contour localization and tracking. When implemented on a focal plane cellular array microprocessor, these algorithms offer real‐time object contour localization and tracking—even at very high frame rates. Three specific methods (Constrained Wave Computing, Pixel Level Snakes and Moving Patch Method) will be described and compared along with their associated hardware–software architectures. Computational complexity, implementation, and performance related issues are discussed on a common platform (ACE‐BOX with the ACEx CNN‐UM chips). In conclusion, a novel architecture is proposed incorporating the best solutions learned from this comparative study. Copyright © 2006 John Wiley & Sons, Ltd.     

Compressive image acquisition in modern CMOS IC design

Compressive sampling (CS) offers bandwidth, power, and memory size reduction compared to conventional (Nyquist) sampling. These are very attractive features for the design of modern complementary metal‐oxide semiconductor (CMOS) image sensors, cameras, and camera systems. However, very few integrated circuit (IC) designs based on CS exist because of the missing link between the well‐established CS theory on one side, and the practical aspects/effects related to physical IC design on the other side. This paper focuses on the application of compressed image acquisition in CMOS image sensor integrated circuit design. A new CS scheme is proposed, which is suited for hardware implementation in CMOS IC design. All the main physical non‐idealities are explained and carefully modeled. Their influences on the acquired image quality are analyzed in the general case and quantified for the case of the proposed CS scheme. The presented methodology can also be used for different CS schemes and as a general guideline in future CS based CMOS image sensor designs. Copyright © 2013 John Wiley & Sons, Ltd.     

微型光谱仪数据采集系统设计与标定

针对目前多采用CCD作为微型光谱仪的光电探测,文中介绍一种利用日本滨松公司的一款高性能线性CMOS图像传感器S11639-01设计了一款微型光谱仪。图像传感器的驱动及光谱仪数据采集系统控制均采用ARM Cortex-M7内核的32位处理器STM32H743芯片。系统硬件电路结构紧凑、数据采集分辨率高、传输实时性好。光谱仪的光路结构由入射狭缝、平场凹面光栅、线阵CMOS探测器组成,该结构相对简单,有利于光谱仪的微型化。采用美国海洋光学标准低压汞灯和卤钨灯对光谱仪进行实验测试,实验所得数据通过波长标定、光谱自动寻峰等技术进行处理,可以得到该系统光谱响应范围220 nm-950 nm,光谱波长标定误差低于0.05 nm,系统最小分辨率1.153 nm,线性度在99.898%以上。     

0.5-/spl mu/m CMOS orthogonal encoding readout cell for active imaging systems

We propose a novel continuous-time simultaneous-readout scheme for active imaging systems based on orthogonal modulation of photodetector signals. The superimposed-continuous-time approach presented here differs from the conventional scheduled-discrete-time scheme in that the photodetector signals are summed in a common bus and read concurrently. We show how that our proposed architecture may be advantageous, particularly in applications where bandwidth requirements for a time-multiplexed scheme are highly demanding. The active readout cell presented here is the kernel of the proposed orthogonal encoding architecture. We describe the cell operation principle, its properties and major design challenges. A 0.5-/spl mu/m CMOS test chip has been fabricated to demonstrate functionality of the readout architecture. Test results show it to be a viable option for highly-integrated active imaging systems.     

A Hybrid Microfluidic/CMOS Capacitive Sensor Dedicated to Lab-on-Chip Applications

A hybrid microfluidic/IC capacitive sensor is presented in this paper for highly integrated lab-on-chips (LoCs). We put forward the design and implementation of a charge based capacitive sensor array in 0.18-mum CMOS process. This sensor chip is incorporated with a microfluidic channel using direct-write microfluidic fabrication process (DWFP). The design, construction and experimental results as well are demonstrated using four different chemical solutions with known dielectric constants. The proposed highly sensitive CMOS capacitive sensor (ap530 mV/fF) along with low complexity DWFP emerges as clear favorite for LoC applications.     

A proposal for high‐performance CCII‐based analogue CMOS design

A novel fully differential CMOS second‐generation current conveyor (CCII) topology is presented. It can be considered as a universal fully differential programmable active element. The circuit operates in moderate inversion region, and features high linearity over a wide input range. Current gain between terminals X and Z can be continuously tuned in a wide range. These features are essential to extend the utilization of CCII‐based circuits to high‐performance VLSI applications. Analogue design based on this new cell is illustrated by various examples. The proposed CCII has been fabricated in a 0.5‐µm CMOS technology and its main performance characteristics have been measured. They are in good agreement with theory and demonstrate that operation in moderate inversion can lead to distortion levels much lower than those achieved in strong inversion. Experimental results for a Tow–Thomas biquadratic filter fabricated on the same chip are also presented, showing continuous frequency tuning in more than a decade. Copyright © 2005 John Wiley & Sons, Ltd.     

LC‐active VCO for CMOS RF transceivers

A novel fully integrated CMOS LC tank VCO is presented. The LC tanks are implemented by exploiting the active circuit ‘boot‐strapped inductor’ (BSI), which behaves like a high‐quality factor inductor. Particularly, the LC tanks have been implemented by introducing a new version of the CMOS BSI circuit, which provides better versatility and design reliability. In order to verify the effectiveness of such an approach, a case study for 5–6 GHz direct‐conversion multi‐standard WLAN transceivers is presented. The VCO has been designed in a 0.35µm standard CMOS technology. The new BSI exhibits a high‐quality factor (higher than 25 over the all frequency range) and provides a high selectivity without introducing a relevant excess of noise, for a better spectral purity and a lower phase noise (PN) of the VCO. The overall VCO circuit consumes 9 mW. The VCO produces an oscillation in the tuning range from 4.91 to 5.93 GHz (nearly equal to 19%). The circuit exhibits a PN of ?129dBc/Hz at 1 MHz of frequency offset from the central frequency (5.4 GHz) and a FOM equal to 189.5 dBc/Hz at 100 kHz and 194.1 dBc/Hz at 1 MHz of frequency offset, respectively. Copyright © 2009 John Wiley & Sons, Ltd.     

X‐ray micrographic imaging system based on COTS CMOS sensors

This paper presents the use of commercial off the shelf CMOS image sensors for the acquisition of X‐ray images with high spatial resolution. The X‐ray images, with application in biology, electronic components inspection, and paleontology research, are obtained with 8‐keV photons from a Cu tube. The quantum efficiency of the detector is estimated using attenuation lengths of photons in the sensor and compared to traditional scintillator conversion layers. The spatial resolution observed with the sensor is limited by the charge redistribution produced after photon interaction with Si.