基于核的信息安全处理芯片可测性设计

从可测性设计角度讨论了信息安全处理芯片的芯片级测试控制器的设计以及相应核的可测性设计.综合结果显示,所设计的芯片级测试控制器所占用的面积代价非常小.     

系统芯片的可测性设计与测试

阐述了系统芯片(SoC)测试相比传统IC测试的困难,SoC可测性设计与测试结构模型,包括测试存取配置、芯核外测试层,以及测试激励源与测试响应汇聚及其配置特性、实现方法与学术研究进展,介绍了基于可复用内嵌芯核的SoC国际测试标准IEEE P1500的相关规约;最后,建议了在SoC可测性设计及测试中需要密切关注的几个理论问题。     

系统芯片的可测性设计

系统芯片SoC可以实现一个系统的功能,为了保证系统芯片的功能正确性与可靠性,在它的设计与制造的多个阶段必需进行测试。由于系统芯片的集成度高,结构和连接关系复杂,使得对它进行测试的难度越来越大,因此需要采用专门的测试结构。本文对系统芯片的可测性设计以及测试结构的设计方法等进行了介绍和综述。     

面向系统芯片的可测性设计

随着集成电路的规模不断增大,芯片的可测性设计正变越来越重要。回顾了一些常用的可测性设计技术,分别讨论了系统芯片（SOC）设计中的模块可测性设计和芯片可测性设计策略。     

系统芯片的测试与可测性设计

随着集成电路制造技术的快速发展，系统芯片SOC(System-on-chip)的应用日益广泛。但SOC设计也遇到诸多挑战，测试就是其中的挑战之一。众所周知，测试问题是SOC设计的一个瓶颈。SOC的测试应包括各内核的测试、用户定义逻辑模块的测试以及各功能块(内核、用户定义逻辑模块)之间连接的测试。因此，SOC的测试是一项重要且耗时的工作。     

异构多核DSP芯片的可测性设计

本文介绍了一款异构多核DSP芯片的可测性设计实现,包含存储器内建自测试、存储器修复、扫描链设计、测试压缩和全速扫描测试。文章首先对芯片架构和可测性设计难点进行了介绍,并制定了全芯片可测性设计的策略,随后介绍了具体的实现,最后给出了覆盖率结果。实验结果表明该设计的测试覆盖率符合工程应用要求。     

基于电力线通信芯片可测性设计的研究实现

集成电路的快速发展,迫切地需要快速、高效、低成本且具有可重复性的测试方案,这也成为可测性设计的发展方向。此次设计基于一款电力线通信芯片,数字部分采用传统常用的数字模块扫描链测试和存储器内建自测试;同时利用芯片正常的通信信道,引入模拟环路测试和芯片环路内建自测试,即覆盖了所有模拟模块又保证了芯片的基本通信功能,而且最大限度地减少了对芯片整体功能布局的影响。最终使芯片良率在98%以上,达到了大规模生产的要求。此设计可以为当前数模混合通信芯片的测试提供参考。     

基于数字电视基带SoC芯片的可测性设计

介绍了基于数字电视基带SoC芯片的可测性设计方案.根据系统中不同模块的特点采取有针对性的可测性设计方案,对片内存储器进行内建自测试;对组合逻辑电路、时序逻辑电路采用近全扫描的测试方案;最后采用IEEE1149.1的控制单元作为芯片可测性设计部分的控制单元,控制芯片的测试功能.经测试,该可测性设计满足设计规划的面积和功耗的要求,并且系统的测试覆盖率达到了99.26%.     

集成芯片的可测性设计技术

主要介绍了三种可测性设计（DFT）技术,分别是：扫描设计（Scan Design）、边界扫描设计（Boundary Scan Design）和内建自测试设计（BIST）。对于这三种设计技术,分别介绍了其原理和设计过程。     

GPS基带芯片中存储器的可测性设计

GPS基带芯片中嵌入的存储器采用存储器内建自测试(Memory Built-in-Self-Test,MBIST)技术进行可测性设计,并利用一种改进型算法对存储器内建自测试电路的控制逻辑进行设计,结果表明整个芯片的测试覆盖率和测试效率均得到显著提高,电路性能达到用户要求,设计一次成功.     

Multiple Scan Chain Design for Two-Pattern Testing

Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.     

Searching for Global Test Costs Optimization in Core-Based Systems

This paper proposes a comprehensive model for test planning and design space exploration in a core-based environment. The proposed approach relies on the reuse of available system resources for the definition of the test access mechanism, and for the optimization of several cost factors (area overhead, pin count, power constraints and test time). The use of an expanded test access model and its concurrent definition with the system test schedule makes it possible the search for a cost effective global solution. Experimental results over the ITC'02 SOC Test Benchmarks show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test planning.     

A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips

This paper deals with the design of SOC test architectures which are efficient with respect to required ATE vector memory depth and test application time. We advocate the usage of a TestRail Architecture, as this architecture, unlike others, allows not only for efficient core-internal testing, but also for efficient testing of the circuitry external to the cores. We present a novel heuristic algorithm that effectively optimizes the TestRail Architecture for a given SOC by efficiently determining the number of TestRails and their widths, the assignment of cores to the TestRails, and the wrapper design per core. Experimental results for four benchmark SOCs show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.     

Enhanced Reduced Pin-Count Test for Full-Scan Design

This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-RPCT for full-scan design, as well as for full-scan core-based design.     

On Concurrent Test of Core-Based SOC Design

In this paper, a method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based System-On-Chip (SOC) designs is presented. The primary objective for concurrent SOC test is to reduce test application time under the constraints of SOC pins and peak power consumption. The methodology used in this paper is not limited to any specific Test Access Mechanism (TAM). Additionally, it can also be applied to SOC budgeting at design phase to predict a tradeoff between test application time and SOC pins needed. The contribution of this paper is the formulation of the problem as a well-known 2-dimensional bin-packing problem. A best-fit heuristic algorithm is adopted to achieve optimal solution.     

一种自动测试游戏机手柄芯片的设计与实现

游戏机手柄芯片的测试一直以来总是采用人工依次测试测点的方法,这种方法费时费力,难以满足批量生产的要求。本文介绍了一种测试游戏机手柄芯片的新方法,以游戏机手柄芯片E2749为例,用单片机实现芯片的自动测试。实践证明,这种方法原理简单,可移植性强,可广泛运用到各类芯片的测试中。