A review of sample backside preparation techniques for VLSI

A review of backside sample preparation techniques is presented. These techniques cover mechanical, chemical and other novel approaches such as laser ablation for ceramic and plastic package opening, silicon thinning and silicon polishing. To illustrate the milling process, we present two challenging backside sample preparation examples on a ceramic package and on a TSOP package.     

A Packaging Solution for Optically Testing Wire-Bonded Chips

In this paper, we describe the design and the experimental characterization of a packaging technique for backside optical testing of chips requiring wirebonding. Optical testing methods, based either on the collection of spontaneous hot-carrier photoemission or on laser stimulation, require an optical access to the active area of the circuit through the backside of the chip, while still providing mechanical support to the thinned die (very fragile), heat sinking capability, power and electrical signals. The proposed package fulfils all these requirements and it can hence be used for picosecond imaging for circuit analysis/time resolved emission measurements, emission microscopy investigations, laser voltage probe, thermal laser stimulation, photoelectric laser stimulation, and other failure analysis methods that require optical access to the transistor level through the silicon backside. The advantages of the new package are its versatility (it can fit different chip sizes), easy handling, low cost, and the fact that it is designed for optical testing and not just for electrical testing. We successfully used the proposed package for optically test chips in advanced complementary metal–oxide–semiconductor technologies (65 nm): measurements at low voltage are possible thanks to the proposed package.      

Evaluation of die edge cracking in flip-chip PBGA packages

Increasing die size and large coefficient of thermal expansion (CTE) mismatch in flip-chip plastic ball grid array (FC-PBGA) packages have made die fracture a major failure mode during reliability testing. Most die fracture observed before was die backside vertical cracking, which was caused by excessive package bending and backside defects. However, due to die edge defects induced by the singulation process and the choice of underfill material, an increasing number of die cracks were found to initiate from die edge and propagate horizontally across the die. In order to improve package reliability and performance, die edge cracking has to be eliminated. An extensive finite element analysis was completed to investigate die edge cracking and find its solutions. A fracture mechanics approach was used to evaluate the effect of various package parameters on die edge initiated fracture. Strain energy release rate was found to be an effective technique for evaluating die edge initiated fracture from singulation-induced flaws. The impact of initial flaw size and a variety of package parameters was investigated. Unlike in die backside cracking, the dominant parameters causing die edge horizontal fracture are more closely related to local effects.     

Ultra-thin pocket embedding package for system in package

Proposed is a new type of packaging technology, `pocket embedding package', using selectively anodised aluminium substrate. In this technology, chips can be embedded inside aluminium substrate so that an ultra-thin and compact type of package can be achieved. A monolithic microwave integrated circuit dice with 120 mum thickness has been successfully embedded inside the substrate with a tolerance of less than 5 mum, and 300 mum of total thickness can be achieved with excellent thermal dissipation     

New non-destructive laser ablation based backside sample preparation method

A new ultra-short pulse laser ablation based backside sample preparation method has been developed. This technique is contact-less, non-thermal, precise, repetitive and adapted to each type of material present in IC packages. Backside preparation examples are presented on a conventional DIL plastic package, a TSOP plastic package with an oversized silicon die and on a DIL ceramic package.     

Thermo-mechanical finite element analysis in a multichip build up substrate based package design

This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the second level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. First, the effect of the positioning of four silicon dice within the MCM package on the warpage of the package is studied. Second, the effect of package dimensions (the heat spreader thickness, the structural adhesive thickness and the substrate thickness) on the maximum residual stress as well as the warpage of the package is performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the Darveaux's approach. A series of parametric study is performed by changing the package dimensions. The results show that the largest die tends to experience highest stresses at its corner and has more influence on the warpage of the package than smaller dice. The results also show the most sensitivity factors that affect the package warpage and the second level solder joint reliability are the substrate thickness and the heat spreader thickness. The structural adhesive thickness has no major effect on the package warpage, the maximum von Mises stress of the package and the second level solder joint reliability.     

Time gating imaging through thick silicon substrate: a new step towards backside characterisation

We propose in this paper a new backside imaging technique. Due to the constant increase ofnumerous metal layers, active areas can no longer be characterized through the frontside component. Nowadays, the most advanced imaging and failure analysis techniques require a modified backside component to allow probing. We propose a technique, where sample preparations are minimized. An optical time gating is used to reduce artefacts coming from the backside surface.     

Wafer level backside emission microscopy: sample preparation

Emission microscopy has been widely adopted as an important tool for analyzing integrated circuit failures from the front surface. More recently, the development of multi-level metallization, flip-chip and lead-on-chip package designs either eliminated or greatly restricted this inspection avenue. An obvious alternative is to inspect from the backside of semiconductors. However, as silicon itself is a light-blocking material, thinning the back surface becomes essential to successful backside emission microscopy (EM). This paper describes a thinning and polishing technique enabling a user to locally thin a defective die on a wafer. This local thinning and polishing allows the wafer to retain its overall mechanical strength to survive the subsequent microprobing while providing a viewing window for EM analysis through the backside.     

A package design technique for size reduction of implantablebioelectronic systems

This paper presents several substrate and package design techniques to minimize the overall size of bioelectronic systems, especially those that will be implanted for in vivo studies. The emphasis is on a new capacitor attachment and a new double-substrate design that have been successfully applied to the packaging of an implantable auditory prosthesis. The entire procedure for this case is described and compared with standard techniques to illustrate the advantages of this new approach in packaging.     

Innovative packaging technique for backside optical testing of wire-bonded chips

This paper describes an innovative packaging technique for versatile backside optically testing chips that require wire bonding. Since both electrical connections to the device under test and optical access through the silicon substrate are required, the sample preparation for testing the chip becomes a key issue. In fact, the thinned die is very fragile and a specific holder is necessary. The proposed package fulfils all these requirements and can be used for PICA measurements, EMMI investigations, LVP, TLS, PLS and other failure analysis methods that require optical access to the transistor level through the silicon backside.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

MCM封装技术中的基板设计与分析

通过采用多芯片组件封装技术,将6种由不同集成电路工艺实现的不同类型的芯片集成在单个封装内,简化了系统设计,实现了产品小型化的目标。同时,还详细给出了Zeni EDA工具下的MCM基板设计流程以及MentorPCB环境下的多芯片组件热分析方法。     

双基机载雷达对地杂波的背面效应及其在GMTI中的应用

本文发现了双基地杂波谱的一个重要特征——背面效应(Backside effect).基于该特征,双基机载雷达的地杂波谱对齐就变得容易许多,从而使空时自适应处理技术在双基模式下的地面动目标检测中更好地发挥作用.本文利用背面效应而提出的基于角度-多普勒谱对齐的旋转谱对齐法,在实验结果中获得了明显的性能提高.     

Physical analysis, trimming and editing of nanoscale IC function with backside FIB processing

Most well established IR-beam based failure analysis techniques and also conventional circuit edit procedures are facing severe challenges resulting from the aggressive downscaling of today’s IC technology. To allow for alternative strategies, novel CE and functional chip analysis techniques have been developed, all being based on backside FIB processing. Additionally, in depth characterization of FIB induced device alterations has shown that a >20% speed gain can be achieved with the proposed FIB thinning procedure. In contrast to all known techniques, this offers trimming of chip internal timing conditions on fully functional samples without being bound to pre-planned fuses or varactors. Based on various experimental results and physical device simulations, this paper briefly reviews the necessary FIB process for which the main focus lies on the FIB induced device alteration. Finally, the novel CE and analysis techniques will be discussed regarding their fields of application, benefits compared to established techniques and theoretical limitations.     

避免发生芯片裂纹的倒装片BGA技术概述

介绍了把断裂力学法应用于倒装片BGA的设计方法。概述了一些关键的材料特性和封装尺寸对倒装片BGA芯片裂纹的影响作用，从而断定基板厚度和芯片厚度是倒装片BGA芯片发生裂纹的两个最重要的因素。     

Soft solder die bonding of multiple die devices

The aim of the work presented in this paper is to study the soft solder die attach of multiple die devices by a multiple pass process. With a multiple pass process we mean a procedure which needs as many die bonder furnace passes as there are different types of dice to be bonded into a package. The main focus of the investigation is on the effect of the necessary multiple furnace passes on the reliability of the soft solder attachment layer. As this behavior may depend on the specific type of device or package (i.e., solder alloy-substrate combination, die size, package geometry), it is analyzed relative to the one of an identical die processed in one single furnace pass. A real package (TO-220) is used as test vehicle and processed on standard equipment. A detailed analysis of the multiple pass process relative to a single pass process with appropriate equipment is performed. It is concluded that a multiple pass process may be slightly less efficient for throughput. However it gives more process flexibility and allows using standard equipment which is available on the market. The result of this investigation strongly supports the feasibility of multiple die devices with a multiple pass process. No reliability limiting influence of the additional furnace passes causing a repeated re-melting and re-solidifying of the solder layer is found. It is, however, necessary to investigate the capability for any other specific device or package again     

Multichip package delamination and die fracture analysis

Multichip mechatronic power packages have been developed in Motorola for automotive applications. Copper heat sink based metal substrates were used to improve thermal and electrical performance. In the early stage of development, mold delamination and die cracking have been observed after assembly. With some mold compound materials, die backside have large delaminated areas, while with other mold compound, delamination stops early but die cracks. Finite element analysis, incorporated with interface fracture mechanics method, has been conducted to understand these phenomena. Impact of mold material properties and package geometry on post-assembly delamination has been evaluated. Good agreements have been obtained between experimental data and the simulation results. The phenomenon of crack branching into the die was also studied. Finite element simulation can be used to predict whether and when the crack at the interface will turn and crack the die. With a thorough understanding of the failure mechanism, both mold delamination and die cracks have been eliminated in the final package development.     

晶圆上测试射频系统级芯片的挑战(英文)

随着无线通讯产业推动芯片集成度的不断提高,系统级封装(SIP)和多芯片组件(MCM)被更多采用,射频系统级芯片(RF-SOC)器件的良品测试已成为一大挑战。这些器件与传统的单晶片集成电路相比,具有更高的封装成本,并且由于采用多个晶片,成品率较低。其结果是进行晶圆上综合测试的成本远超过最终封装后测试器件的成本。此外,一些IC制造商销售裸晶片以用于另一些制造商的SIP和MCM中,这就要求发货的产品必须是良品。以蓝牙射频调制解调芯片为例,讨论了RF-SOC器件良品晶片(KGD)的测试难点和注意事项。对此样品,除了在晶圆上进行射频功能测试的难点,还有同时发射和测量数字、射频信号的综合问题。此外对被测器件(DUT)用印制线路板布线的难点,包括晶圆探针卡的设置及装配进行探讨。还介绍了选择探针测试台、射频晶圆探针卡和自动测试设备(ATE)时需考虑的因素。并以晶圆上测试的系统校正,包括难点和测试方法,作为结尾。这颗蓝牙射频调制解调芯片的实际测试数据也会被引用,以佐证和加深文章中的讨论。     

An investigation of thermal enhancement on flip chip plastic BGApackages using CFD tool

This paper demonstrates the advantage of applying Predictive Engineering in the thermal assessment of a 279 inputs/outputs (I/Os), six-layer, depopulated array flip chip PBGA package. Thermal simulation was conducted using a computational fluid dynamics (CFD) tool to analyze the heat transfer and fluid flow in a free convection environment. This study first describes the modeling techniques on a multilayer substrate, thermal vias, solder bumps, and printed circuit board (PCB). For a flip chip package without any thermal enhancement, more than 90% of the total power was conducted from the front surface of the die through the solder ball interconnects to the substrate, then to the board. To enhance the thermal performance of the package, the heat transfer area from the backside of the die needs to increase dramatically. Several thermal enhancing techniques were examined. These methods included a copper heat spreader with various thicknesses and with thermal pads, metallic lid, overmolded with and without a heat spreader, and with heat sink. An aluminum lid and a heat sink gave the best improvement; followed by a heat spreader with thermal pads. Both methods reduced thermal resistance by an average of 50%. Detailed analyses on heat flow projections are discussed     

Application of layout overlay for failure analysis

New layout overlay techniques have been developed based on standard image correlation techniques to support failure analysis in modern microelectronic devices, which are critical to analyze because they are realized in new technologies using sub-μm design rules, chemical mechanical polishing techniques CMP and auto-routing design techniques. As the new techniques are realized as an extension of a standard CAD-navigation software using standard image format “TIFF”, which is available at all modern FA-equipment, these techniques can be used for all modern failure analysis methods. Examples of application are given for circuit modification using Focused Ion Beam (FIB), for supporting preparation from the backside and for fault localization using emission microscopy.